High-voltage analog performance with low-voltage digital devices [100 V dense operational amplifier fabrication]

A new circuit technique is described, yielding typical analog system voltage (36 V) operation from a circuit fabricated with low-voltage (LV/SUB CEO/=12-15 V) transistors. Such transistors can be fabricated in one-quarter the area of conventional higher breakdown devices, leading to great reductions in chip size and improved frequency performance due to decreased parasitics. This technique can be used to build complex systems combining high-voltage analog and dense digital circuitry on the same chip, with standard digital processing and without sacrificing analog performance. An extension of the technique uses a typical linear (LV/SUB CEO/=40 V) process to build high voltage (80-100 V) circuits. A 100 V op amp was designed and breadboarded with standard linear kit parts.     

A monolithic telephone subscriber loop interface circuit

An integrated circuit that interfaces a subscriber loop with the digital telephone exchange has been produced with conventional high-voltage IC technology. The monolithic SLIC controls DC loop current, converts signal transmission from two-wire to four-wire, and suppresses longitudinal induction. Bias control circuitry automatically reduces standby power when subscriber equipment is detected on-hook. High-voltage circuit techniques maintain performance when the supply voltage exceeds the n-p-n transistor BV/SUB CE0/, and circuit partitioning with two discrete transistors yields manageable junction temperature and an economical 102/spl times/112 mil die size.     

A dual current feedback op amp in CMOS technology

A CMOS circuit configuration implementing a current feedback or transimpedance op amp (CFB op amp) is presented. The architecture of the circuit is derived from similar bipolar CFB op amps. The properties of the CMOS implementation are similar to those of its bipolar counterparts, i.e., a high slew rate and a bandwidth which is independent of the closed-loop gain when the op amp is used with current feedback. Further, it is shown how two CFB op amps can be connected to achieve a non-slew-rate-limited voltage-mode op amp.     

Leveraged Current Mirror Op Amp

A small change to the standard current mirror op amp configuration is shown to improve performance, with few, if any, disadvantages. Adding a pair of fixed current sources allows reduced operating-point current in the output stage, while the resulting leveraging effect increases slew rate. For equal total power dissipation, the new configuration improves DC gain and gain-bandwidth (GBW) over conventional current-mirror and folded cascode op amps, as shown by hand analyses and SPICE simulations. Also, because of increased input stage transconductance, the new configuration reduces thermal and flicker noise.     

A high precision micropower operational amplifier

An operational amplifier configuration implemented as a true micropower high precision op amp is described. It includes a well controlled and predictable DC biasing network that is insensitive to variations in temperature, supply voltages, and process. Also, it permits single supply operation. Excellent DC precision characteristics, comparable to or better than the very best precision op amps currently available, are realized yet at micropower levels. By simply increasing the biasing currents, a version of this design operates in general purpose applications without any degradation in its high precision characteristics. Thus, the AC performance levels of general purpose op amps are attained at a fraction of supply current. This device is fabricated using a standard bipolar IC process; an ion-implanted JFET is added to simplify biasing.     

A complete monolithic 10-b D/A converter

A monolithic 10-b plus sign D/A converter has been developed that incorporates all necessary circuit functions including voltage reference and internally compensated high-speed output op amp in a single 82/spl times/148 mil chip. A unique logic switch and current source configuration achieves 0.05 percent nonlinearity with /spl plusmn/10 V compliance current output option as well as true or complementary binary coding. The design constraints and area requirements for scaling of current source emitter areas are reduced by using a new active current-splitting technique. The circuit features a 1.5 /spl mu/s settling time voltage output and sign-magnitude coding.     

Bandwidth optimization of a low power,high speed CMOS current op amp

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2µm CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128M H z at a supply voltage of 3V and a supply current of 25µA. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.     

一种折叠共源共栅运算放大器的设计

折叠共源共栅运放结构的运算放大器可以使设计者优化二阶性能指标,这一点在传统的两级运算放大器中是不可能的。特别是共源共栅技术对提高增益、增加PSRR值和在输出端允许自补偿是有很用的。这种灵活性允许在CMOS工艺中发展高性能无缓冲运算放大器。目前,这样的放大器已被广泛用于无线电通信的集成电路中。介绍了一种折叠共源共栅的运算放大器,采用TSMC 0.18混合信号双阱CMOS工艺库,用HSpice W 2005.03进行设计仿真,最后与设计指标进行比较。     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

Precise Voltage to Frequency Converter for Telemetry Applications of Strain Gage Pressure Transducers

A voltage to frequency converter suitable for telemetric applications of strain gage pressure transducers is described and analyzed. The circuit uses a voltage reference IC and a temperature dependent op amp bias current to achieve zero pressure offsets less than 3 torr over a 25°C temperature range and a 1 volt supply voltage range.     

Power loss-oriented evaluation of high voltage IGBTs and multilevel converters in transformerless traction applications

The low-frequency line transformer in todays ac rail vehicles suffers from poor efficiency and a substantial weight. Future traction drives may operate directly from the mains without this transformer. A feasible concept for a transformerless drive system consists of series connected medium voltage converters applying modern high-voltage insulated gate bipolar transistors (HV-IGBTs). In a first design step, the switching characteristics and losses of 6.5-kV IGBTs are compared to 3.3-kV and 4.5-kV IGBTs which are already commercially used in traction applications. Based on the considered HV-IGBTs, the properties of multilevel converters are analyzed and their applicability to the transformerless system is evaluated. The paper focusses on a loss analysis of the converters. Reliability aspects and harmonic spectra are briefly discussed. Taking these design aspects into account, the three-level neutral point clamped converter turns out to be a reasonable solution to realize line and motor converter modules in a transformerless traction system.     

Implementation of active distributed RC anti-aliasing/smoothing filters

The design of an active distributed RC filter is described for use as an anti-aliasing/smoothing filter in a PCM channel bank filter. A new filter configuration (known as a Rauch filter) has been chosen which uses the op amp in inverting configuration with a zero common mode signal and thus results in improved high-frequency attenuation characteristics along with good power supply rejection. A conventional Sallen and Key configuration with distributed RC elements is also discussed.     

A new high-voltage analog-compatible I/SUP 2/L process

A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V.     

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time.     

A new three-terminal thyristor-based high-power switchingconfiguration with high-voltage current saturation

A new high-voltage power switch configuration having thyristor based on-state current conduction together with high-voltage current saturation characteristics is described. Current saturation is obtained in the new thyristor structure by diverting part of the base current at a predesigned current level to bring the NPN and PNP transistors comprising the thyristor out of their regeneratively-coupled conduction mode. The concept has been experimentally verified by fabricating 1200 V, 175 A devices     

Low-power SITL IC

The SITL (static induction transistor logic), which operates in the bipolar mode, has the smallest PD (power delay) product in silicon technology because of the use of an extremely pure epitaxial layer. In this paper, as SITL device is which the gate and drain are self-aligned is described, centering on the DC characteristics and operation limit. It is concluded that the drain current of SIT is limited by the thermionic emission mode in a low-current region of about 1 nA over a wide temperature range, and that logic operation is limited by the effective current gain /spl beta//SUB eff/ in the low-power region. Designing SITL suitably for wide temperature and power range, the authors have developed a monolithic watch IC having an oscillation frequency of 2 MHz and a current consumption of 3.5 /spl mu/A, and including bipolar circuitry on the same chip.     

Influence of substrate current on hold-time characteristics of dynamic MOS IC's

The charge hold-time characteristics of three-transistor-type MOS memory cells were investigated. It was observed that, at first, the holding-node voltage V/SUB G/ decreased slowly, due to junction leakage current. However, when V/SUB G/ reached a value determined by the sense-inverter dc supply voltage and external load resistance, V/SUB G/ fell rapidly. The onset value of the rapid drop coincided well with the value of V/SUB G/ that caused substrate current to flow in the sensing inverter. It is suggested that an extremely small amount of substrate current I/SUB sub/ arrives at the holding node and that positive feedback between V/SUB G/ and I/SUB sub/ causes the rapid drop of V/SUB G/. A simple analysis was pursued to estimate the transport probability /spl alpha/ of the substrate current I/SUB sub/ arriving at the holding node. It was also observed that the hold-time characteristics of neighboring physically independent cells were degraded by substrate current generated by one cell. The transport probability between these holding nodes and the driver transistor generating the I/SUB sub/ was estimated as a function of the separating distance.     

Predicting the Effect of Pulsed Ionizing Radiation on Operational Amplifiers

The response of IC operational amplifiers (op amps) to pulsed ionizing irradiation is studied theoretically and experimentally. The major mechanisms of the radiation response are covered. The contributions of main op-amp stages to the output-voltage response are analyzed. The ionization-induced failure of an op amp is traced to its intermediate stages. It is established that the recovery time depends on the type of compensation employed. A block-model approach is proposed as a method for the prediction of transient radiation responses. Ways to define the performance index of an op amp exposed to pulsed ionizing radiation are discussed.     

High-gain microwatt composite cascode op amps

This article discusses the composite cascode stage, both single-ended and differential, operating in the weak inversion or moderate inversion region. The gain of the MOS composite cascode differential stage can exceed 100,000?V/V, a figure that has never been reported in the literature. For low-frequency applications, this configuration can be used to fabricate op amps that have high-gain, low-power and low-nonlinear distortion. Two different architectures, both having two gain stages are reported. The first op amp uses the Widlar architecture to achieve a gain of 117?dB, a power dissipation of 110?µW and uses a compensation capacitor of only 3.5?pF. The second op amp uses a class AB stage for the second and final stage and utilises the parasitic capacitance at the output of the first stage for compensation. This self-compensating op amp has a gain of 110?dB and a power dissipation of 21?µW.     

High-gain gaas mesfet op amp

A gain enhancement technique for GaAs MESFET op amps is presented. It uses positive feedback to cancel the output conductance between the driver and active load transistors in a common-source amplifier configuration. An op amp using this technique was implemented in a 1-µm non-self-aligned GaAs MESFET process. The op amp exhibited a dc gain of 60 dB and a unity-gain frequency of 840 MHz.Please address all correspondence to C.A.T. Salama.