Second-order sigma-delta modulation for digital-audio signalacquisition

The authors compare the second-order sigma-delta (ΣΔ) modulator to several alternative modulator architectures in the context of digital-audio signal acquisition. Design details and experimental results are presented for a 1 μm CMOS implementation that does not require error correction or component trimming to achieve virtually ideal 16 b performance at a conversion rate of 50 kHz. The experimental modulator is a fully differential circuit that operates from a single 5 V power supply and does not require the use of precision sample-and-hold circuitry. With an oversampling ratio of 256 and a clock rate of 12.8 MHz, the modulator achieves a 98 dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 94 dB. Measurements and simulations of discrete noise peaks in the output spectrum that result from limit-cycle oscillations are also presented and discussed     

A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dBdynamic range

A CMOS ΣΔ modulator for speech coding with continuous-time loopfilter is presented. Compared to switched-capacitor implementations, the relaxed bandwidth requirements of the active elements of the loopfilter reduce the power consumption. Furthermore, the need for an antialiasing filter at the modulator input is eliminated. A fourth-order, 64× oversampling ΣΔ modulator for application in portable telephones was designed and shows 80 dB dynamic range over the 300-3400 Hz voice bandwidth. Its input is directly connected to the microphone (maximum 40 mV_RMS). Total harmonic distortion (THD) is below -70 dB at 95 μA current consumption from a 2.2 V supply voltage. The active die area of the modulator is 0.5 mm² in a standard 0.5-μm CMOS process     

Architecture, design, and test of continuous-time tunableintermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP ΔΣ) modulators. Bandpass modulators sampling at high IFs (~100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP ΔΣ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f_T) of 80 GHz and a maximum frequency of oscillation (f_MAX) of about 130 GHz. Operating from ±5-V power supplies, a fabricated 180-MHz IF fourth-order ΔΣ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (~1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (~60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements     

A double-sampling pseudo-two-path bandpass ΔΣ modulator

A double-sampling pseudo-two-path bandpass ΔΣ modulator is proposed. This modulator has an output rate equal to twice the clock rate, uses n/2 operational amplifiers (op-amps) for an nth-older noise transfer function, and has reduced clock feedthrough in the signal path band. The required clocks can be simpler to implement than the conventional pseudo-two-path techniques. The measured signal-to-noise ratio and dynamic range of the fourth-order double-sampling pseudo-two-path bandpass ΔΣ modulator in a 30-kHz bandwidth at a center frequency of 2.5 MHz (at a clock frequency of 5 MHz) are 62 and 68 dB, respectively     

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

CMOS fully-differential bandpass ΣΔ modulator usingswitched-current circuits

The authors present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. It is the first reported integrated circuit realisation of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z¹→-z²) to a second-order lowpass modulator. It has been realised using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency     

A stereo multibit ΣΔ DAC with asynchronous master-clockinterface

A two-channel multibit ΣΔ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1° phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-μm DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm×4 mm     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic rangeusing the switched-opamp technique

The design and implementation of a very low supply voltage/low power ΔΣ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop ΔΣ modulator. The chip is implemented in a 0.7-μm CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 μW. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB     

A high-resolution multibit ΣΔ ADC with digitalcorrection and relaxed amplifier requirements

A second-order multibit ΣΔ (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2-μm CMOS process. The excellent measured linearity and high S/(N+D) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture     

The design of sigma-delta modulation analog-to-digital converters

The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta (ΣΔ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Σ2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3-μm CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm², and has achieved a measured dynamic range of 89 dB     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz     

Granular quantization noise in a class of delta-sigma modulators

The trend toward digital signal processing in communication systems has resulted in a large demand for fast accurate analog-to-digital (A/D) converters, and advances in VLSI technology have made ΔΣ modulator-based A/D converters attractive solutions. However, rigorous theoretical analyses have only been performed for the simplest ΔΣ modulator architectures. Existing analyses of more complicated ΔΣ modulators usually rely on approximations and computer simulations. In the paper, a rigorous analysis of the granular quantization noise in a general class of ΔΣ modulators is developed. Under the assumption that some input-referred circuit noise or dither is present, the second-order asymptotic statistics of the granular quantization noise sequences are determined and ergodic properties are derived     

A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpassΣΔ modulator for AM signal A/D conversion

This paper presents a CMOS 0.8-μm switched-current (SI) fourth-order bandpass ΣΔ modulator (BP-ΣΔM) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z^-1 →-z^-2) to a 1-bit second-order low-pass ΣΔ modulator (LP-ΣΔM). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz     

Quadrature bandpass ΔΣ modulation for digital radio

A quadrature bandpass ΔΣ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward “complex A/D conversion” of an image reject mixer's I and Q, outputs. Quadrature bandpass ΔΣ modulators provide superior performance over pairs of real bandpass ΔΣ modulators in the conversion of complex input signals, using complex filtering embedded in ΔΣ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-μm CMOS process is 2.4×1.8 mm²      

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/Dconversion

The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (ΣΔ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1-μm CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming     

A 1.8-V MOSFET-only ΣΔ modulator using substrate biaseddepletion-mode MOS capacitors in series compensation

A low-voltage high-linearity MOSFET-only ΣΔ modulator for speech band applications is presented. The modulator uses substrate biased MOSFETs in the depletion region as capacitors, linearized by a series compensation technique. A second-order fully differential single-loop architecture has been realized in a conventional 0.25-μm digital n-well CMOS process without extra layers for capacitors. An SNDR of 72 dB and an SNR of 77 dB is obtained with 8-kHz signal bandwidth at an oversampling ratio of 64. The circuit consumes about 1 mW from a single 1.8-V power supply and occupies a core area of 0.08 mm²     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with aself-calibrated multibit DAC

Delta-sigma (ΔΣ) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date