Improved “K” type seven-level switched capacitor inverter topology with Self-voltage balancing

This paper proposes an improved “K” type seven-level switched capacitor inverter topology. The proposed topology consists of eight active switches, one floating capacitor, and two dc-link capacitors. The floating capacitors are charged and discharged in each half-cycle to maintain the capacitor voltage with the same value of the input voltage. The floating capacitor voltage is self-balanced, and the output voltage is 1.5 times higher than the input voltage. To prove the superiority of the proposed topology, it is compared with the existing seven-level inverters in terms of maximum voltage stress on the switch and required the number of power components. The simulation and experimental validation are carried out for 1.6 kW, 50 Hz using a laboratory-based setup with a switching frequency of 5 kHz. The results are discussed highlighting the performance of the proposed topology for the dynamic load variations at different modulation indices. Both simulation results and experimental results have good agreement in terms of voltage balancing of flying capacitor.     

Advanced power conditioner using sinewave modulated buck–boost converter cascaded polarity changing inverter

This paper presents an advanced power converter employs a sinusoidal voltage absolute value tracking buck–boost DC–DC converter in the first power processing stage and a polarity changing full-bridge inverter in the second stage. The proposed power conversion system has the capability of delivering good quantitative and qualitative sinusoidal output current and voltage waveforms with good output voltage regulation. Consequently, the complete voltage regulator system, which is mainly suitable for new energy generation systems as well as energy storage systems, can be constructed compactly and inexpensively without DC link electrolytic capacitor. Also, the paper presents an auxiliary passive resonant circuit for soft switching operation. Simulation results using PSIM software are presented to verify the operation principles and feasibility of the proposed power conversion system. Finally, these results are verified by means of an experimental prototype.     

Modeling and analysis method of fractional-order buck–boost converter

In this paper, the equivalent small parameter method (ESPM) is used to establish the nonlinear mathematical model of the fractional-order buck–boost converter in continuous current mode (CCM), and the analytical expression of approximate steady-state period of converter state variable is obtained by using equivalent small parameter method and combining with harmonic balance principle. The Matlab/Simulink is used to construct the fractional-order capacitance and inductance and to build the circuit model as well as the simulation model of fractional-order buck–boost converter. Moreover, the simulation results of Oustaloup circuit model and numerical simulation model are compared with those of ESPM model to verify the validity and accuracy of the ESPM. The model is simulated by changing the orders of the capacitor and inductor to obtain the influence rule of the order of fractional element on harmonic characteristics of the state variables.     

A high-efficient fast-transient boost converter with adaptive on-time controlled and zero-current–detection techniques

A high-efficient fast-transient boost converter with adaptive on-time controlled and zero-current–detection techniques is presented in this paper. The adaptive on-time controlled technique can rapidly reach desired output voltage in two to three switching cycles. The proposed boost converter uses a zero-current–detector to detect and prevent the negative inductor current issue that can decrease the light-load power consumption and increase the light-load efficiency. Therefore, this new configuration accelerates transient response and improves light-load efficiency of the boost converter. The proposed boost converter has been fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm Complementary Metal-Oxide-Semiconductor (CMOS) 1P6M technology, and the chip area is only 1.148 × 1.187 mm (including personal assistant devices [PADs]). The input voltage range is from 0.5 to 1 V, and the output voltage is 1.8 V. The measured transient response time is about 2 and 3 μs, when the load current is changed from 5 to 300 mA and from 300 to 5 mA, respectively. The converter's operating frequency is 1 MHz, the maximum output current is 300 mA, and the peak power efficiency is 91.6% under 200-mA load current. The experimental results confirm that the light-load efficiency of the converter can be increased 11%.     

A single-phase p-type ac–ac converter with reduced components count and high boost factor

This paper proposes a new single-phase direct step-up ac–ac converter by modifying the p-type impedance source. It provides a high boost factor as well as high efficiency, while only six parts are required to design it, involving just two bidirectional power switches. A safe commutation method has been applied to power switches to make the converter snubber-free and high efficient. Input and output harmonic filters are no longer required since input and output currents variate continuously with small ripple and low total harmonic distortion (THD). The proposed topology only modulates the output voltage amplitude, not the phase and frequency, so the output frequency is identical to the input frequency and constant. Thus, it can be utilized in step-up conversion applications, like inductive power transmission from low ac voltage sources. Input and output have the same ground, which is a good protective feature. In this paper, the operating principle of the converter is demonstrated. Experimental results have been represented to evaluate the performance of the converter. For this purpose, an experimental prototype has been fabricated. Results are investigated and compared with other previous step-up ac–ac converters. Results confirm the theory, operating principle, and performance of the converter.     

A fast time–frequency transform based differential relaying scheme for UPFC based double-circuit transmission line

This paper presents a new differential relaying scheme for a mutually coupled, double circuit transmission line in presence of Unified Power Flow Controller (UPFC) in the line. The process starts at retrieving the three phase current signals at both ends of the transmission line synchronously and processing it though the time–frequency transform such as Fast Discrete S-Transform to derive the spectral energy content of the current signals. The differential spectral energy of current signals (difference between the spectral energy of the current signal at the sending and receiving ends, respectively) of the respective phases of transmission line is used to register the fault pattern. The proposed approach includes fault detection and classification along with identification of the fault section with respect to UPFC location in one of the double-circuit transmission line. The extensive test results indicate that the proposed differential relaying scheme is highly reliable in registering fault patterns in UPFC based transmission line including wide variations in operating parameters of the power network.     

Short term hydro–wind–thermal scheduling based on particle swarm optimization technique

Hydro–wind–thermal scheduling is one of the most important optimization problems in power system. An aim of the short term hydrothermal scheduling of power systems is to determine the optimal hydro, wind and thermal generations in order to meet the load demands over a scheduled horizon of time while satisfying the various constraints on the hydraulic, wind and thermal power system network. In this paper we present optimal hourly schedule of power generation in a hydro–wind–thermal power system applying PSO technique. The simulation results inform that the proposed PSO approach appears to be the powerful to minimize fuel cost and it has better solution quality and good convergence characteristics than other techniques.     

A charge sharing–based switching scheme for SAR ADCs

This paper presents an energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed scheme employs charge recycling method to keep the capacitor arrays free of transitional energy between bit generations except reset phase. In comparison with the conventional switching scheme, the proposed one achieves 100% transitional energy saving without considering reset phase. In addition, configuration of a 10-bit SAR ADC shows that the proposed switching scheme reduces the capacitor area by 25% compared with the conventional switching scheme.     

Nanoelectronic circuit elements based on nanoscale metal–molecular networks

Journal of Computational Electronics - We report a density functional non-equilibrium Green's function study of the electronic transport properties of nanoscale networks composed of Au metal...     

Poisson–Nernst–Planck model for an ionic transistor based on a semiconductor membrane

In this paper we developed a Poisson–Nernst–Planck model of an ionic current flowing through a nanopore in a layered solid-state membrane made of a single highly-doped \(n\) -Si layer sandwiched between two thick oxide layers which we call the ionic transistor. We studied this layered membrane for a range of source-drain voltages while keeping the gate (the semiconductor membrane) voltage fixed at a certain value, which was later varied too. We find that for this ionic transistor to be effective in controling the ion fluxes through the nanopore, the gate voltage must be kept relatively large. Another solution could be to increase the surface negative charge on the membrane or to replace the outer oxide layers with the semiconductor material, such as the \(p\) -Si material. The developed model can be applied to study ionic filtering and separation properties of membranes of different composition and nanopore geometries.     

Simulation of a current-mode controlled DC–DC boost converter in chaotic regime evaluating different simulation methods

The main objective of the paper is to evaluate and demonstrate different simulation tools for the simulation of switch-mode power supplies. Also the modelling process from the design engineers point of view is considered. A current-mode controlled DC–DC boost converter in chaotic regime is chosen as an application example because it offers an up-to-date and challenging simulation problem. Simulations carried out with the conventional Spice circuit simulator, switched state-space model implemented in the Matlab/Simulink simulation environment and Power System Blockset extension are compared with each other and also partly with analytical predictions and the results obtained with discrete-time two-dimensional mapping. Experiments are performed to conclude the validity of the simulation results.     

Adaptive-biased sense-FET–based inductor-current sensor for 10-MHz buck converter

A sense field effect transistor (FET)–based inductor-current sensor for buck converters is introduced in this paper. The proposed current sensor adopts and realizes piecewise-linear adaptive bias to maintain consistent bandwidth and phase margin in the sensor's control loop throughout a wide range of load currents. Moreover, the specially designed turn-on/off process of switches is introduced together with the sole gain–boosted amplifier to avoid the sharp transitions in the sensed peak and valley currents during the deadtime zone of synchronous buck converters. Simulation results of the proposed sensor show an 11.6-dB rise in direct current (DC) gain at light load (approximately 200 mA) and 21° improvement in phase margin at heavy load (approximately 2 A), compared with the traditional structure with fixed-bias current. Furthermore, the variation in the unity gain bandwidth of the proposed structure across the whole load range is 12.8 times lower than that of the traditional designs.     

Analysis,modeling, and implementation of a new transformerless semi-quadratic Buck–boost DC/DC converter

This paper presents a novel transformerless semi-quadratic buck-boost converter (SQBuBoC). In the proposed SQBuBoC, two power switches with simultaneous operation are used and a higher step-up/step-down voltage conversion ratio is achieved compared with the traditional buck-boost, Cuk, single-ended primary-inductor converter, and Zeta converters. The positive polarity of the output voltage, along with low ripple continuous input current and common ground between the source and the output voltages, are some features that make the suggested topology more suitable for many applications with wide range of output voltage such as photovoltaic systems. Moreover, the total voltage stress across the power switches in this converter is lower than the cascade boost, and the traditional buck-boost converters led to power MOSFETs selection with lower drain-source ON resistance (R_ds) and efficiency improvement. All the steady-state analysis and comparisons in continuous conduction mode (CCM) are discussed in details. In addition, to study the low frequency behavior of the SQBuBoC by means of the state-space averaging technique, the small and large signal models of this converter in CCM are presented. Finally, the SQBuBoC analysis is justified using experimental results of a 50 W step-up 25 V to 120 V and a 28 W step-down 25 V to 14 V laboratory prototypes.     

A second-generation voltage conveyor (VCII)–based simulated grounded inductor

In this paper, an implementation of a simulated grounded inductor (SGI) based on a recently developed active building block called second-generation voltage conveyor (VCII) is proposed. The proposed SGI employs two VCIIs, two resistors, and one grounded capacitor, which is preferred when integration is involved. More importantly, unlike most of the other previously reported SGIs, this one is free from any restrictive matching conditions. A complete analysis of nonidealities along with sensitivity treatment by considering parasitic impedances and nonideal gains of the VCII are performed. A simple VCII circuit is designed to be used in the implementation of the proposed SGI. To support the presented theory, Pspice simulation results using 0.18-μm CMOS technology parameters and supply voltage of ±0.9 V are provided. On the basis of the achieved results, the proposed SGI operates in a good agreement with an ideal inductor. The power consumption is only 0.65 mW, and the parasitic series impedance is approximately 191.9 Ω. The applicability of the proposed SGI is tested by using it in a standard second-order high-pass RLC filter.     

PID controller for automatic voltage regulator using teaching–learning based optimization technique

The present work presents teaching–learning based optimization (TLBO) algorithm as an optimization technique in the area of tuning of the classical controller installed in automatic voltage regulator (AVR). The proposed TLBO algorithm is applied with an aim to find out the optimum value of proportional integral derivative (PID) controller gains with first order low pass filter installed in the AVR. The voltage response of the AVR system, as obtained by using the proposed TLBO based PID controller with first order low pass filter, is compared to those offered by the other algorithms reported in the recent state-of-the-art literatures. The advantage of using this control strategy may be noted by providing good dynamic responses over a wide range of system parametric variations. For on-line, off-nominal operating conditions, fast acting Sugeno fuzzy logic technique is applied to obtain the on-line dynamic responses of the studied model. Furthermore, robustness analysis is also carried out to check the performance of the designed TLBO based PID controller. An analysis, based on voltage response profile, has been investigated with the variations of the model parameters. The simulation results show that the proposed TLBO based PID controller is a significant optimization tool in the subject area of the AVR system. The essence of the present work signifies that the proposed TLBO technique maybe, successfully, applied for the AVR of power system.     

A new H∞ based PSS design using numerator–denominator perturbation representation

A new H_∞ PSS design method which uses the numerator–denominator perturbation representation and includes the partial pole placement technique and a new weighting function selection method is proposed. This overcomes certain conventional H_∞ PSS design algorithm limitations. A robust PSS has been successfully designed by treating the highly non-linear characteristic of the power system as model ‘uncertainty’. The design is verified to have better performance for a wide range of system operating conditions when compared with the conventional PSS design.     

Optimal reactive power dispatch using hybrid Nelder–Mead simplex based firefly algorithm

This paper presents a novel hybrid algorithm combining Firefly Algorithm (FA) and Nelder Mead (NM) simplex method for solving power system Optimal Reactive Power Dispatch (ORPD) problems. The ORPD is a very important aspect of power system operation and is a highly nonlinear, non-convex optimization problem, consisting of both continuous and discrete control variables. Like many other general purpose optimization methods, the original FA often traps into local optima and in order to overcome the shortcoming, in this paper, an efficient local search method called NM simplex subroutine is introduced in the internal architecture of the original FA algorithm. The proposed Hybrid Firefly Algorithm (HFA) avoids premature convergence of original FA by exploration with FA and exploitation with NM simplex. The proposed method is applied to determine optimal settings of generator voltages, tap positions of tap changing transformers and VAR output of shunt capacitors to optimize two different objective functions; such as minimization of real power loss and voltage deviations. The program is developed in Matlab and the proposed hybrid algorithm is examined on two standard IEEE test systems for solving the ORPD problems. For validation purpose, the results obtained with the proposed approach are compared with those obtained by other methods. It is observed that the proposed method has better convergence characteristics and robustness compared to the original version of FA and other existing methods. It is revealed that the proposed hybrid method is able to provide better solutions.     

Partial fraction expansion–based realizations of fractional-order differentiators and integrators using active filters

Approximations of the fractional-order differentiator and integrator operators s^±r are proposed in this work. These approximations target the realization of these operators using standard active filter transfer functions. Hence, circuit implementations in integrated circuit form or in discrete component form are significantly facilitated. Complementary metal-oxide-semiconductor (CMOS) realizations of the proposed approximations are given and validated via simulations using the AMS 0.35 μm CMOS technology, while experimental results using operational amplifier circuits are tested and confirm the proposed theory.     

Thevenin’s equivalent based P–Q–V voltage stability region visualization and enhancement with FACTS and HVDC

Voltage source converter based Flexible Alternating Current Transmission System (FACTS) devices are considered to be key technology to alleviate voltage instability. This paper examines the enhancements in feasible operating P–Q–V space with FACTS and HVDC. Thevenin’s equivalent at the load bus is applied to draw P–Q–V curve (shows the boundary of the maximum real, reactive power and the minimum voltage magnitude) and area of voltage stability region (AVSR) in a three-dimensional diagram. A visualization framework for voltage stability region in MATLAB environment is implemented to study the impact of FACTS (SVC, STATCOM, and TCSC) and HVDC. The best possible location of shunt controllers is obtained using AVSR and index ‘L’. The line stability indices are calculated and compared to verify the weakest line for installation of series controllers. The inclusive study has been performed on IEEE-14 and IEEE-30 bus systems. The results show the enhancement in area of voltage stability region in all cases with maximum in case of HVDC.     

Outage data analysis of utility power transformers based on outage reports during 2002–2009

Statistical analysis of failures and forced outages of power transformers constitute an important basis for asset management of these transformers. Results of the statistical analysis can be used, for example, to enhance utility reliability, influence transformer design and technology, and improve maintenance and condition monitoring practices. In addition, various methods for transformer reliability evaluation require that the expected values of component outage rates, outage durations, and repair durations be known. In this paper, outage data are obtained from the Egyptian Electricity Transmission Company (EETC). This work presents outage data analysis over eight years, from 2002 to 2009, for 1922 (average number) transformers in voltage populations ranging from 33 kV to 500 kV and MVA rating from 5 MVA to 500 MVA. Forced outages due to correct and false action of transformer’s protection systems are carefully considered. Outage data analysis is conducted according to two basic phases. In the first phase, failure and repair analysis of transformers is performed while in the second phase impact of transformer outages on customers is assessed. Percentage average number of failures (%AANF) and annual average repair time (AART) per transformer are used to represent the failure and repair data of power transformers. Two indicators are used to represent the impact of transformer outages on customer interruptions. These indicators are the annual average interrupted MW (AAIMW) and annual average customer-interruption duration (AACID). A summary of the main outcomes of the work presented in this paper is provided in the conclusions’ section; however, it is worthy to be mentioned here that the fire-fighting systems are responsible for the highest number of false trips in all voltage subpopulations except the 220 kV subpopulation where the dominant cause of false trips is the busbar protection. Therefore, it is recommended to improve the maintenance and design of this protection equipment to reduce the failure rate of power transformers.