Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

Electronically tunable low-component-count current-mode biquadratic filter using dual-output current followers

In this paper, a realization of a current-controlled three-input single-output current-mode universal biquadratic filter using dual-output current followers (DO-CFs) as active components is described. Based on the use of the current-controlled conveyor working as the DO-CF, the proposed circuit employs only two DO-CFs and two grounded capacitors that provide the advantage of an electronic tuning capability and is of special interest from the IC fabrication point of view. By suitably selecting three input signals, the filter can realize all of the standard biquadratic filtering functions, i.e., lowpass, bandpass, highpass, bandstop and allpass, all at a high impedance output which enables easy cascading in the current-mode operation. The natural angular frequency (ω _o ) and the bandwidth (BW) of the proposed circuit can be tuned independently and electronically over a wide range by adjusting the external bias currents. In addition, no critical component matching conditions are required for all the filter response realizations, and both active and passive sensitivities are low. PSPICE simulation results are used to confirm the characteristics of the proposed circuit.     

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

In this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μ m CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.     

Analog circuit design by nonconvex polynomial optimization: Two design examples

We present a framework for synthesizing low‐power analog circuits through global optimization over generally nonconvex multivariate polynomial objective function and constraints. Specifically, a nonconvex optimization problem is formed, which is then efficiently solved through convex programming techniques based on linear matrix inequality (LMI) relaxation. The framework allows both polynomial inequality and equality constraints, thereby facilitating more accurate device modelings and parameter tuning. Compared to traditional nonlinear programming (NLP), the proposed methodology exhibits superior computational efficiency, and guarantees convergence to a globally optimal solution. As in other physical design tasks, circuit knowledge and insight are critical for initial problem formulation, while the nonconvex optimization machinery provides a versatile tool and systematic way to locate the optimal parameters meeting design specifications. Two circuit design examples are given, namely, a nested transconductance(G_m)–capacitance compensation (NGCC) amplifier and a delta–sigma (ΔΣ) analog‐to‐digital converter (ADC), both of them being the key components in many electronic systems. Copyright © 2008 John Wiley & Sons, Ltd.     

LC‐active VCO for CMOS RF transceivers

A novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ‘boot‐strapped inductor’ (BSI), which behaves like a high‐quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability. In order to verify the effectiveness of such an approach, a case study for 5–6 GHz direct‐conversion multi‐standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high‐quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9 mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93 GHz (nearly equal to 19%). The circuit exhibits a PN of ?129dBc/Hz at 1 MHz of frequency offset from the central frequency (5.4 GHz) and a FOM equal to 189.5 dBc/Hz at 100 kHz and 194.1 dBc/Hz at 1 MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd.     

Harmonic fold back reduction at the N‐path filters

In this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N‐path filters, without increasing the input reference clock (f_CLK ) frequency. The HFB at the N‐path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M‐of‐N‐path filter has been proposed that behaves like an M × N‐path filter in terms of HFB problem; however, the f_CLK frequency of this structure is the same as an N‐path filter. To demonstrate the feasibility of the proposed idea, a 3‐of‐4‐path filter is designed, and its characteristics are compared with 4‐path and 12‐path filters by simulation. Impacts of different non‐idealities like clock‐phase error, mismatch, and parasitic capacitance are investigated. The transistor‐level implementation of this filter is performed in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass‐band gain of 17 dB, tuning range of 0.2–1.2 GHz, −3 dB bandwidth of 25 MHz, quality factor of 8–48, 18 dB out‐of‐band rejection, 16 dB rejection of the third harmonic of switching frequency (f_s ), and the noise figure of 4.35 dB (using ideal G_m cells) and 6.95 dB (for practical G_m cells). The strongest harmonic folding to the filter pass‐band occurs around 11f_s with the attenuation of 23.8 dB. Each G_m cell draws about 12.4 mA from 1.8 V supply, and the out‐of‐band IIP3 and P _{1 dB,CP} are 17 and 4 dBm, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

A high output power and low phase noise GaN HEMT VCO with array of switchable inductors

This paper presents cross‐coupled voltage‐controlled oscillators (VCOs) involving array of switchable inductors (i.e., N  = 1 and N  = 2 switchable inductors) and implemented using gallium‐nitride high electron mobility transistors on Si substrate technology for worldwide interoperability for microwave access applications. Band selection and coarse frequency tuning were achieved using the array of switchable inductors, whereas fine tuning was controlled using varactors. Two bands were obtained using the one‐stage switchable inductor VCO operating in the ranges 3.41–3.57 GHz and 3.85–3.94 GHz. The VCO output power (P_out) was 21.8 dBm at 3.57 GHz from a 10‐V power supply. Four continuous bands were obtained using the two‐stage switchable inductors VCO operating in the range of 3.16–3.4, 3.25–3.64, 3.48–3.71 and 3.64–3.9 GHz, respectively. An additional band was generated by fine‐tuning the inductance through mutual coupling between the transmission line and one of the inductors. The proposed two‐stage switchable inductors VCO provided a 21% tuning range at frequencies ranging with a control voltage ranging from 12 to 20 V, a low phase noise of −123 dBc/Hz at a 1‐MHz offset from a 3.3‐GHz carrier and a P_out of 21 dBm at 3.5 GHz from a 10‐V power supply. Copyright © 2017 John Wiley & Sons, Ltd.     

基于多级线性最优方法的多频段直流附加阻尼控制器设计

通过总体最小二乘-旋转不变技术辨识出系统振荡模式和降阶模型,对应系统的不同振荡模式,利用巴特沃斯带通滤波器将控制器分解为多个频段,基于多级线性最优方法控制和阿克曼公式,设计出带状态观测器的多频段高压直流附加阻尼控制器,为不同频段的振荡模式提供阻尼,实现同时抑制低频振荡和次同步振荡的功能。同时,在PSCAD实际系统中进行了仿真实验,并对比线性二次型最优控制和比例积分控制,证明了本文所设计控制器的有效性和鲁棒性,对于工程实践具有一定意义。     

一种适用于GaN器件的谐振驱动电路

针对氮化镓(GaN)器件,传统的驱动电路是电压源型驱动,在高频下充放电回路中的寄生电感会引起栅源电压振荡,超过GaN器件的栅源耐压值,损坏GaN器件。采用谐振驱动(RGD)电路是解决上述传统驱动存在的问题的有效途径之一,利用LC谐振,在GaN器件开通和关断时提供一条低阻抗箝位路径,减小栅源电压的振荡,提供一个稳定的栅源电压。详细分析了RGD电路的工作原理,同时设计制作了1 MHz的Boost变换器原理样机,并给出了实验结果。     

Performance Evaluation of Power Oscillation Damping Controller—Firefly Algorithm Based Parameter Tuning

This paper presents the performance evaluation of power oscillation damping controller based on firefly algorithm (FA) parameter tuning. The power system stabilizer (PSS), unified power flow controller (UPFC), and static synchronous series compensator (SSSC) are tuned with FA by minimizing integral time multiplied by absolute error (ITAE) as an objective function. An integrated multi-stage linear quadratic regulator – power oscillation damping UPFC/SSSC has been proposed with precise tuning of control parameters which results in overall states' oscillation damping as compared to other classical methods. It has been observed that the proposed control structure damps the oscillations adequately and is modular in design methodology. The sample power system comprising six areas has been considered to demonstrate the effectiveness of the concept. The software has been developed based on the proposed work by the authors and the MATLAB code has been generated in R2009b version. The states' inter-relation which has been shown with eigenvalues reflects a better regulation and the step response is also validated.     

Design and analysis of 0.9 and 2.3-GHz concurrent dual-band CMOS LNA for mobile communication

A complementary metal-oxide-semiconductor (CMOS) dual-band low-noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3 GHz of frequencies. The dual-band operation is achieved by adding a modified notch-filtering path in the wideband LNA. The modified notch-filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency. Sustainability of the LNA under process corner variation and temperature variation are examined, and it is found to be suitable for the application. The proposed LNA is designed at 90-nm technology in Cadence Virtuoso with 0.5 and 0.6-V supply. The post-layout simulation shows 22 dB of gain (S₂₁), 2 dB of Noise Figure (NF), and −5.5 dBm of IIP3 at the high band. In the low band, 24 dB of S₂₁, 2.7 dB of NF, and −6.65 dBm of IIP3 are reached. The circuit consumes 5.2 mW of power and 0.0918 mm² of area. The efficiency of the LNA is estimated by the figure of merit, and comparable results are secured in the proposed work.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

低场核磁共振系统的脉冲功率激励源

本文提出了一种实用可靠、经济简单的低场核磁共振系统的脉冲功率激励源设计方案.通过理论和实验结果验证了开关功率放大的互补输出电路可以满足低场核磁共振系统中功率激励源的特殊要求.给出了功率MOSFET在开关频率2MHz以下的驱动电路设计.该方案已应用在低场核磁共振系统中的脉冲激励源上,具有输出效率高、频率范围宽、调谐方便,有利于核磁共振实验时谐振点搜寻等优点.     

A genetic‐based neuro‐fuzzy controller for blind equalization of time‐varying channels

This paper presents a neuro‐fuzzy network (NFN) where all its parameters can be tuned simultaneously using genetic algorithms (GAs). The approach combines the merits of fuzzy logic theory, neural networks and GAs. The proposed NFN does not require a priori knowledge about the system and eliminates the need for complicated design steps such as manual tuning of input–output membership functions, and selection of fuzzy rule base. Although, only conventional GAs have been used, convergence results are very encouraging. A well‐known numerical example derived from literature is used to evaluate and compare the performance of the network with other equalizing approaches. Simulation results show that the proposed neuro‐fuzzy controller, all parameters of which have been tuned simultaneously using GAs, offers advantages over existing equalizers and has improved performance. From the perspective of application and implementation, this paper is very interesting as it provides a new method for performing blind equalization. The main contribution of this paper is the use of learning algorithms to train a feed‐forward neural network for M‐ary QAM and PSK signals. This paper also provides a platform for researchers of the area for further development. Copyright © 2008 John Wiley & Sons, Ltd.     

A class of digitally programmable nth‐order filters

A family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.     

New current–voltage transferring device with different metals

A new concept of an electrical shunt with different materials (aluminum and copper) has been developed to be used as an alternative current measurement device. The device provides better current measurement characteristics compared with the conventional current measurement devices such as a shunt resistor with an ammeter or the multiple shunts consisting of molybdenum having a low temperature coefficient and a Rogowski coil with an integrated circuit. The currents in several electrical circuits have been measured using the developed current–voltage transferring device (CVTD) as voltages between the aluminum and copper elements. The measured voltages (V_m) are proportional to measuring currents (I_m), which is shown as the following the experimental equation V_m [mV] =kI_m [A], in which k is a coefficient depending on the configuration of the CVTD. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

A fully soft switched high step-up SEPIC-boost DC-DC converter with one auxiliary switch

This paper proposed a new single-ended primary inductor converter (SEPIC)-boost DC-DC converter that uses only one auxiliary switch to create soft switching condition for all semiconductor devices. The auxiliary circuit comprises one power switch (S_a), one resonant inductor (L_r), one resonant capacitor (C_r), and one diode (D_o2). The auxiliary switch (S_a) controls the resonance during switching instants. The converter has simple structure and its control circuit remains pulse width modulation (PWM). Besides, the proposed converter has high voltage gain without using any transformer or coupled inductors. In addition, the auxiliary switch is not located in the main power path. Moreover, using soft switching techniques is the best way for reducing the size, weight, and volume of the converter. Furthermore, reduction of input inrush current and voltage stress for the main switch is obtained by using SEPIC-boost structure. A laboratory prototype converter is designed and implemented. The experimental results presented confirm the theoretical and features of the proposed converter.     

Switched current circuit using fixed gate‐potential transistor and automatic tuning circuit

Clock feedthrough (CFT) error is one of the most important problems for switched current (SI) circuits. This paper proposes a SI circuit which can reduce CFT error drastically. The proposed circuit will theoretically reduce both signal‐dependent and independent errors by using CMOS switches under a fixed and appropriate bias. Although conventional circuits based on a similar idea need operational amplifiers or additional capacitors, our proposed circuit requires only MOSFETs. The proposed circuit can reduce CFT current with less power consumption and chip area compared to those of conventional circuits. An automatic tuning circuit, which controls the gate potential appropriately, is also proposed. Simulation results demonstrate the effectiveness of the proposed circuits. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 21–29, 1999     

A waveform generator circuit for extra low‐frequency CMOS micro‐power applications

This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.