Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments

As transistor feature size is scaling down, the probability of charge sharing in a space-radiation environment increases because of the reduced distance between adjacent transistors. The single-event multiple-node upset (SEMNU) caused by charge sharing is a major source of data errors in high-density static random-access memory (SRAM). In this paper, a radiation-hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD-12T, RSP14T, SEA14T, We-Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC-14T cell saves 8.47%, 91.34%, 162.71%, -20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read-delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write-delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation-intensive space environment.     

One-sided 10T static-random access memory cell for energy-efficient and noise-immune internet of things applications

This paper presents a one-sided 10-transistors static-random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy-efficient SRAM cells are necessary to raise the battery lifetime. The bit-cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate-wrap-around (GWA) carbon nanotube (CNT)-gate-diffusion input (GDI) technique and only one-bit line to perform both read and write operations to minimize active power consumption. The proposed bit-cell uses a transmission gate network and write-assist schemes to significantly improve the write-ability and stack read-decoupling technique to enhance hold-/read-stability. Moreover, a memory mini-array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write- and read-yield parameters for the proposed SRAM bit-cell are about 22% and 13% better than counterpart bit-cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit-cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit-cell in the real-world application, a memory array architecture with an online (or off-chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy-efficient and noise-immunity IoT platforms.     

Design and statistical analysis of low power and high speed 10T static random access memory cell

Static random access memory (SRAM)-based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub-nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45-nm complementary metal-oxide-semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N-controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, -41.6%, and 52.9% compared with 6T, NC, 10T-sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.     

一种高可靠性智能型避雷器在线监测系统的设计

金属氧化物避雷器(MOA)监测系统在智能变电站中得到越来越多的应用,但在工程运行中也存在一些问题,如运行不可靠、监测数据不准确、集成度差和系统故障率偏高等。为了解决上述问题,对智能型金属氧化物避雷器在线监测系统进行了改进设计,从系统整体构架、传感器设计、安装方式、在线监测智能电子设备(IED)设计等方面开展工作,提供了一种测量精度高、计算灵活、适应性及可扩展能力强的高可靠性避雷器在线监测系统方案,并全面支持基于光纤链路的通用面向对象变电站事件(GOOSE)、采样测量值(SMV)以及站控层制造报文规范(MMS)通信,可更好地满足智能变电站现场应用要求。     

一种高精度六谱线插值FFT谐波与间谐波分析方法

加窗插值快速傅里叶变换(Fast Fourier Transform, FFT)算法因其便于在嵌入式系统实现而被广泛应用于电力系统谐波检测,可改善因非同步采样和非整周期截断造成的频谱泄漏与栅栏效应,提高FFT分析的精确度。针对目前常用的加窗插值算法存在的不足,在分析五项最大旁瓣衰减(Maximum-Sidelobe-Decay, MSD)窗频谱特性的基础上,提出一种基于五项MSD窗六谱线插值FFT的谐波与间谐波分析算法。该算法利用紧邻峰值谱线频点的六条谱线进行加权运算,充分考虑峰值频点左右对称谱线所蕴含的信息以提高分析精度。通过数据拟合求出窗函数对应的插值修正公式,简化了运算过程。仿真结果表明,五项MSD窗六谱线插值FFT算法设计实现灵活,抑制频谱泄漏效果极好。相比于其他常见的四谱线插值FFT算法,该算法具有更高的谐波、间谐波检测精度。     

一种高性能无线传感器网络节点的设计与实现

为了降低节点功耗和在发射功率不变的前提下增大其通信距离,在节点设计原则基础上,提出一系列解决方案来减少节点电路板不必要的能量损耗;选用巴伦匹配的传输线使得同等发射功率下节点通信距离增大.设计实现了一种基于处理器ATmega128L和射频芯片CC2420的低功耗、低成本和小型化的无线传感器网络节点.对该节点和MICAz节点进行性能测试实验,结果表明,该节点较MICAz节点功耗小、同等发射功率下通信距离远.     

高性能升压型DC-DC电源变换器的设计与实现*

利用STM32F103RBT6单片机为主控芯片,采用推挽式拓扑结构及脉冲宽度调制技术,设计制作了一款高性能升压型DC DC电源变换器。该电源变换器的直流输入电压范围为15~25 V,直流输出电压可调范围为30~36 V,最大输出电流为1 A。实验测试结果表明,设计的电源变换器具有较好的负载调整率和电压调整率,输出电压波纹较低,转换效率高,并且具有输出电压的步进调整和测量、显示以及过流、过压保护等功能,在中小型升压型开关电源中具有较好的应用价值和发展前景。     

一种新型高性能开关电源的设计与实现

采用单端反激式变换器结构和电流连续工作模式,设计并实现了一种基于LD7532A PWM控制芯片的高效率、高功率密度和高可靠性的开关电源装置。该电源装置的交流输入电压为90 V～264 V,工作频率65 kHz,输出功率40 W,输出电压19 V。该装置的实验测试结果表明,所设计的开关电源装置的效率在85. 7%左右,空载损耗低于0. 3 W,满载输出电压纹波值小于60 mV,输出电压稳定。     

基于OPNET的广域测量系统仿真与通信延时性能分析

广域测量系统对实时性要求严格,而通信延时是影响实时性的重要因素。通信延时作为广域测量系统延时的重要组成,带有不确定性,因此成为其通信性能研究的重点和难点。对广域测量系统的通信设备、通信业务和通信网络拓扑进行建模,并依此对电力系统稳态工况、故障工况和网络设备故障工况三类场景进行仿真。由此得到在不同工况下广域测量系统的通信延时大小,从而评估分析该系统的现状和瓶颈。为广域测量系统的研究分析提供了新方法,同时为其规划与建设提供了参考意见。     

电力系统过程网络CAN总线实时性仿真与分析

CAN总线在电力系统过程网络取得广泛应用,总线的实时性是衡量网络性能的重要指标。对CAN总线传输时延进行分析,指出影响CAN总线端到端时延的主要因素。根据CAN总线非破坏逐位仲裁的特点,基于OPNET软件使用队列模型对CAN总线数据传输进行建模仿真,以一个电站过程网络为对象,得到了考虑位填充和不同网络速率情况下数据帧的最大时延和网络平均负载流量,验证了模型的正确性。针对CAN总线强制优先级导致低优先级数据传输时延过大的缺点,使用分类动态优先级方法,在保证不同类别数据实时传输的同时,保证同一类别数据传输的公平性,提高网络的利用率。结果表明,该仿真模型基本反映了CAN传输时延特点。     

高性能数字接收机FPGA设计与实现

针对多模移动通信标准测试的需求,设计一款可广泛应用于多模综测仪的数字接收机.根据带通采样原理直接对153.6 MHz的QPSK/TD-SCDMA等中频信号进行采样,在FPGA中实现高效数字下变频、移相滤波、多速率抽取、成型滤波和符号同步等功能,以正交I、Q信号输出便于后续DSP对其进行软件算法解调和处理.实验结果表明,该方案能有效减少数字下变频资源消耗、增强接收通道的线性动态范围、提高模数转换器的有效分辨率、改善通道矢量解调指标,适合作为多模宽带数字中频接收机的实施方案.     

一款实用高性能开关电源的设计与实现

采用有源功率因数校正(APFC)及同步整流技术设计了一款实用反激式开关电源装置.样机实验结果表明,所设计的APFC开关电源的功率因数达到0.952～0.989,整个电源系统的效率高于85.8%,且总谐波电流畸变率＜3.75%,电磁污染程度较低,因而此装置具有实用推广价值.     

大型火电厂锅炉“四管”爆漏原因分析及防治对策

针对大型锅炉“四管”爆漏问题,结合宁夏中宁发电有限责任公司WGZ1112／17．5—3型亚临界参数汽包炉的运行情况。分析了“四管”爆漏的原因,从管理和技术角度提出了有效的防治对策。     

基于互相关分析的低雷诺数涡街流量计设计

针对常规涡街流量计难以测量雷诺数在5 000~20 000内流量的问题,研制测量低雷诺数流量的涡街流量计,以扩展量程比。重新设计涡街流量计一次仪表,以满足互相关分析的要求。充分利用两个压电传感器输出信号的相似性,采用互相关分析方法,实现低雷诺数流量的测量。提出一种基于互相关分析快速计算时延的方法,保证仪表的实时性。采用三次样条插值的方法,大大减小较低的采样频率对延迟时间测量精度的影响。以低功耗单片机MSP430F6459为核心,研制成功低功耗、两线制涡街流量变送器。水流量标定结果表明,该涡街流量计量程下限所对应的雷诺数为6 649,测量精度为1级。     

风力机叶片的分段直前后缘设计技术与应用

目前风力机叶片的气动设计方法主要依据简化风车模型与Glauert旋涡理论,但这两种方法得到的叶片在叶根及叶尖弦长过大,在叶根附近扭曲严重,对整体性能及加工制造不利。文章在Glauert旋涡理论设计方法基础上,给出了一种前后缘分段直线化设计技术及其在风力机叶片的气动外形设计中的应用。利用该技术对1MW风力机叶片进行气动设计与计算,得到了风力机在浆矩角可调及风速变化情况下的气动性能预测结果,为风力机叶片多参数化建模及优化设计方法奠定了理论基础。     

C-MMC型电力电子变压器直流故障分析与保护方法研究

对模块化多电平换流器(Modular Multilevel Converter,MMC)型电力电子变压器的拓扑结构及实现原理进行介绍。分析了在采用半桥子模块的MMC中发生中压直流母线双极短路故障后的电流流通路径,以及其不能实现直流故障闭锁的原因。为解决上述问题,选取箝位双子模块代替半桥模块,并分析了其故障电流流通路径和故障闭锁原理。但由于箝位双子模块在直流故障闭锁后可能出现子模块过电压问题,为此,提出了电力电子变压器隔离级延时闭锁的策略,并分析了MMC闭锁后在该策略下隔离级闭锁前的故障电流流通路径。最后,通过PSCAD仿真平台对箝位双子模块的闭锁功能和隔离级延时闭锁策略进行了仿真验证。     

基于树莓派的EtherCAT主站设计与性能分析

本文设计了一种基于树莓派的轻量化EtherCAT主站及其测试系统。在测试系统上,通过多通道侦听器,测量了多个并行运行主站的性能参数;借助于软硬件时间戳,测量了轮询/中断、单/多核等多种模式下的时延抖动;还测量了数据帧在协议各层的时延与抖动。基于树莓派的EtherCAT主站采用VxWorks操作系统,在实现过程中重点对系统内核配置、网卡驱动、报文处理、应用层软件等方面进行了优化。经测试,该主站性能稳定,在125μs循环周期下的抖动约6μs,可满足工业现场数据采集、楼宇自动化、AGV控制等需求。     

基于Matlab的孤立逆变源的设计及故障分析

分布式发电(distributed generation,DG)是一种高效、清洁的发电方式,以其具有投资少、发电方式灵活、可与环境兼容等优点,在微电网中得到了广泛的应用。但是,在向配电网引入分布式发电的同时也带来了一些问题。在微电源并入电网时,如果在并入过程中微电源出现单相、两相或三相故障,就会对电网的稳定性带来不利的影响。通过Matlab软件,建立仿真实验平台,针对以上故障问题进行了仿真分析。     

电动变桨距系统超级电容后备电源测试装置设计与应用

针对目前广泛应用的电动变桨距系统超级电容后备电源性能难以测试的问题,设计了一种简单可行的厂内后备电源测试装置,并利用某种具体型号的电容进行测试。测试结果表明,该装置能够对超级电容后备电源的性能（电容变化电压、顺桨时间、电机电流等）做出测试,根据该测试进行后备电源的设计,该设计能够满足变桨系统的顺桨要求,进而确保风力发电机组的安全运行。     

Design and performance analysis of a 700‐kW wound‐rotor BDFIG for ship shaft generator application

In this paper, a 700‐kW brushless doubly fed induction generator (BDFIG) is designed for stand‐alone ship shaft generator application. Based on the principle of tooth harmonics and sinusoidal winding structure, a multi‐pitch unequal‐turn‐coil wound rotor is adopted to reduce harmonic contents and couple the two stator windings effectively. The performance analyses of a prototype BDFIG with two/four pole pairs are presented. The magnetic fields, air‐gap flux densities, and current densities with full load at different shaft speeds of the prototype machine are investigated. Simulation analysis and experimental tests verify that the output capability and the efficiency of the prototype machine could meet the design requirements of a 700‐kW generator and that the wound rotor structure is suitable for high‐power brushless doubly fed machines. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.