零电压零电流开关PWM组合式三电平变换器

提出一种零电压零电流开关PWM组合式三电平变换器，它由半桥三电平变换器与全桥变换器组合而成。该变换器所有开关管的电压应力均为输入电压的一半；可以在很宽的负载范围内实现MOSFET的ZVS，在很宽的负载范围内实现IGBT的ZCS；输出滤波器上高频分量小，可以大大减小输出滤波器的体积；可以在三电平和两电平两种工作模式下切换工作，输出整流二极管的电压应力小。该文分析该变换器的工作原理，介绍了其特点，并给出实验结果。     

Improved control‐to‐output characteristics of a PWM buck‐boost converter

An indirect control variable for improving the control‐to‐output characteristics of a Pulse Width Modulation (PWM) buck‐boost converter is introduced in this letter. The voltage gain and the small‐signal model of the buck‐boost converter are reviewed. The actual voltage command at one input of the PWM comparator is from the proposed indirect control variable and the peak value of the high‐frequency PWM carrier. The resulted voltage gain function appears proportional to this indirect control command. Also the dependence of the DC gain of the control‐to‐output transfer function on the duty cycle is eliminated. Experimental results conform well to the theoretical analysis. Copyright © 2010 John Wiley & Sons, Ltd.     

一种适用于可变阻感负载的交流调压器

提出了一种适用于可变阻感负载的单相交流调压方案.采用PWM控制的AC/AC降压变换器实现了对负载电压的调节.宽幅电流检测确保了负载容量变化时输出电压和输出电流的质量和稳定性.还给出了变负载情况下输出滤波器的设计方法.1kVA样机的实验结果表明,提出的方案在不同容量的阻感负载下均能精确调压,输出电压和输出电流质量均能满足理论要求.     

A power efficient buck‐boost converter by reusing the coil inductor for wireless bio‐implants

In this paper, a buck‐boost converter circuit for wireless power transfer via inductive links in bio‐implantable systems is presented. The idea is based on reusing the power receiver coil to design a regulator. This method employs five switches to utilize the coil inductor in a frequency other than the power‐receiving signal frequency. Reusing the coil inductor decreases the on‐chip regulator area and makes it suitable for bio‐implants. Furthermore, in the proposed technique, the regulator efficiency becomes almost independent of the coil receiving voltage amplitude. The proposed concept is employed in a buck‐boost regulator, and simulation results are provided. For a 10 MHz received signal with the amplitude variation within 3 ~ 6 V and with the converter switching rate of 200 kHz, the achieved maximum efficiency is 78%. The proposed regulator can also deliver 10 μA to 4 mA to its load while its output voltage varies from 0.6 to 2.3 V. Simulations of the proposed converter are performed in Cadence‐Spectre using TSMC 0.18 μm CMOS technology. Copyright © 2017 John Wiley & Sons, Ltd.     

A novel active‐clamp zero‐voltage‐switching buck‐boost converter

An active‐clamp zero‐voltage‐switching (ZVS) buck‐boost converter is proposed in this paper to improve the performance of converter in light load condition. By employing a small resonant inductor, the ZVS range of switches could be adjusted to very light load condition. Moreover, 2 clamping capacitors are added in the converter to eliminate the voltage spike on the switches during transition. The operating principle of the proposed converter is analyzed, and the optimal design guide for full range ZVS is also provided. A 60‐W output prototype is experimentally built and tested in laboratory to verify the feasibility of proposed converter. The measured results show the critical ZVS operation of power switches at 1 and 0.7‐W output power for buck and boost mode, respectively. The peak conversion efficiency is up to 92.3%.     

A detailed analytical analysis of a passive resonant snubber cell perfectly constructed for a pulse width modulated d.c.–d.c. buck converter

In this paper, a detailed analytical analysis of a passive resonant snubber cell that is perfectly constructed for a pulse width modulated (PWM) d.c.-d.c. buck converter is proposed. This snubber cell provides a larger overall efficiency and a wider load range than most of the active snubber cells presented previously, and has a simple structure and low cost. The operation principles and a detailed steady-state analysis of a PWM buck converter implemented with this snubber cell are presented. The theoretical analysis is verified with a prototype of a 5-kW and 50-kHz insulated gate bipolar transistor-(IGBT)-PWM buck converter. All of the semiconductor devices in the converter operate under soft switching conditions. Additionally, at 80% output power, the overall efficiency of the proposed soft switching converter is increased to about 98% from the value of 91% in its counterpart hard switching version.     

Direct voltage regulation of DC–DC buck converter in a wide range of operation using adaptive input–output linearization

In this paper, an adaptive nonlinear controller is designed for voltage control of the DC–DC buck converter in both continuous and discontinuous conduction modes. The proposed controller is developed based on input–output linearization, which is robust and stable against converter load changes, input voltage variations, and parameter uncertainties. In the proposed approach, all the converter parameters, namely input voltage, load resistance, and other parasitic elements of the power circuit, are assumed to be uncertain and estimated using a suitable Lyapunov function. Using a stand‐alone TMS320F2810 digital signal processor from Texas Instruments, some simulations and experimental results are obtained to verify the proposed control approach. The results are in good agreement and prove the effectiveness and capability of the controller over a wide range of operations. Also, advantages of the designed nonlinear regulator are indicated in comparison with a pulse width modulation (PWM)‐based sliding mode controller. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

改进PWM开关变换器输出电压动态特性的控制新方法

ＰＷＭ开关变换器的输出电压动态特性与设计的控制策略有关。本文提出一种新的非线性控制方法,使得ＰＷＭ开关变换器的输出电压,在负载干扰和电源电压干扰下,具有优良的动态特性。以降压型变换为例,计算机仿真结果证明该控制策略的优良性能。     

Fast‐transient DC‐DC converter using a high‐performance error amplifier with a rapid output‐voltage control technique

This letter presents a method for improving the transient response of DC‐DC converters. The proposed technique replaces the conventional error amplifier with a combination of two different amplifiers to achieve a high loop gain and high slew rate. In addition, a rapid output‐voltage control circuit is employed to further reduce the recovery time. The proposed technique was applied to a four‐phase buck converter, and the chip was implemented using a 0.18‐μm CMOS process. The switching frequency of each phase was set at 2 MHz. Using a supply voltage of 2.7–5.5 V and an output voltage of 0.6–1.5 V, the regulator provided up to 2‐A load current with maximum measured recovery time of only 6.2 and 6.5 μs for increasing and decreasing load current, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

Design and implementation of an interleaved soft‐switching converter with output voltage doubler

An interleaved pulse‐width modulation (PWM) converter with less power switches is presented in this paper. The buck type of active clamp circuit is used to recycle the energy stored in the leakage inductor of a transformer. The zero voltage switching (ZVS) turn‐on of power switches is realized by the resonance during the transition interval of power switches. At the secondary side of transformers, two full‐wave rectifiers with dual‐output configuration are connected in parallel to reduce the current stresses of the secondary windings of transformers. In the proposed converter, power switches can accomplish two functions of the interleaved PWM modulation and active clamp feature at the same time. Therefore, the circuit components in the proposed converter are less than that of the conventional interleaved ZVS forward converter. The operation principle and system analysis of the proposed converter are provided in detail. Experimental results for a 280 W prototype operated at 100 kHz are provided to demonstrate the effectiveness of the proposed converter. Copyright © 2008 John Wiley & Sons, Ltd.     

A high-efficient fast-transient boost converter with adaptive on-time controlled and zero-current–detection techniques

A high-efficient fast-transient boost converter with adaptive on-time controlled and zero-current–detection techniques is presented in this paper. The adaptive on-time controlled technique can rapidly reach desired output voltage in two to three switching cycles. The proposed boost converter uses a zero-current–detector to detect and prevent the negative inductor current issue that can decrease the light-load power consumption and increase the light-load efficiency. Therefore, this new configuration accelerates transient response and improves light-load efficiency of the boost converter. The proposed boost converter has been fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm Complementary Metal-Oxide-Semiconductor (CMOS) 1P6M technology, and the chip area is only 1.148 × 1.187 mm (including personal assistant devices [PADs]). The input voltage range is from 0.5 to 1 V, and the output voltage is 1.8 V. The measured transient response time is about 2 and 3 μs, when the load current is changed from 5 to 300 mA and from 300 to 5 mA, respectively. The converter's operating frequency is 1 MHz, the maximum output current is 300 mA, and the peak power efficiency is 91.6% under 200-mA load current. The experimental results confirm that the light-load efficiency of the converter can be increased 11%.     

基于复合控制的LLC谐振变换器轻载纹波优化

为提高LLC谐振变换器输出电压稳定性,改善轻载工况下输出电压纹波,提出了一种复合控制策略以实现全桥LLC变换器全负载范围的稳定电压输出。此种控制策略混合了有限双极性PWM控制与PFM控制,轻载时采用有限双极性PWM控制模式,重载时采用PFM控制模式,以此实现零电压开关,有效提高了LLC谐振变换器的效率,使得输出纹波大大减小。最后,通过实验验证了分析的正确性以及所提复合控制策略的有效性。     

新型谐波消除交流电压调节器的研究

提出一种新型谐波消除交流电压调节器方案,采用斩波方式AC-AC降压变换器结合输出串联补偿升压变压器实现负载电压的双向调节。其中降压变换器应用先进的谐波消除脉宽调制技术以实现交流系统侧所有低次谐波成分在输出负载端的消除,且其调制函数可以根据简便的前馈方法从输入电压信号中直接求解,因此具有良好的动态响应特性和实践可行性。2kVA样机的实测结果表明,所提出的方案在交流电压精确调节以及谐波抑制方面具有良好的表现。     

Analysis and Implementation of an Interleaved ZVS Converter with High Input Voltage

An interleaved half‐bridge converter is presented for high input voltage application. The features of the proposed converter are zero voltage switching (ZVS) turn‐on for all active switches, ripple current reduction at output side, load current sharing and load voltage regulation. Two half‐bridge converters connected in series and two split capacitors are used to limit the voltage stress of each power switch at one‐half of input DC bus voltage. Thus, active switches with low voltage stress can be used at high input voltage application. On the other hand, the output sides of two half‐bridge converters are connected in parallel to share the load current and reduce the current stresses of the secondary windings and the rectifier diodes. Since two half‐bridge converters are operated with interleaved pulse‐width modulation (PWM), the output ripple current can partially cancel each other such that the resultant ripple current at output side is reduced and the size of output inductors can be reduced. In each half‐bridge converter, asymmetrical PWM scheme is used to regulate the output voltage. Based on the resonant behavior by the output capacitance of MOSFETs and the leakage inductance (or external inductance) of transformers, active switches can be turned on at ZVS during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The proposed converter can be applied for high input voltage applications such as three‐phase 380‐V utility system. Finally, experiments based on a laboratory prototype with 960‐W rated power are provided to demonstrate the performance of proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.     

基于遗传算法的Buck变换器控制优化研究

介绍了根据负载变化的情况,以减少输出电压的变化为目标来获取降压转换器的控制器器件值参数整定的方法.传统的方法是获取优化的相位裕度,结果使输出电压的响应稳定度略有改进.而利用遗传优化算法使相位裕度成为调整参数,并且电路元件值被认为是直接调整参数给予优化,使降压转换器的输出电压具有非常优良的控制特性.     

加钳位二极管的零电压开关PWM三电平直流变换器

零电压开关PWM三电平直流变换器 (ZVSPWMTL变换器 )利用变压器的漏感和开关管的结电容可以实现开关管的零电压开关 ,但是输出整流管仍然存在反向恢复带来的尖峰电压。为了解决这个问题 ,提出一种新的ZVSPWMTL变换器 ,它在基本的ZVSPWMTL变换器中增加两个二极管 ,消除了输出整流管的电压振荡 ,同时保留基本的ZVSPWMTL变换器的所有优点。分析了这种新的变换器的工作原理 ,并在一个 6 0 0W的原理样机上进行了验证 ,最后给出了实验结果。     

A new bridgeless buck PFC rectifier

In this study, a new bridgeless buck power factor correction (PFC) rectifier is presented. The proposed buck PFC rectifier is designed to operate in the discontinuous conduction mode (DCM). Because of the DCM operation, the control scheme of the proposed buck PFC rectifier is simple and easy, and the reverse recovery problem of the diodes can be alleviated. Because the input current follows the input voltage naturally, the current loop circuit is not required. Thus, only the traditional voltage‐mode control is employed to sense the output voltage, and a suitable control effort for the proposed buck PFC rectifier is generated to drive the power switches. Consequently, the output voltage of the proposed buck PFC rectifier can be kept at a desired value. Finally, the mathematical deductions and experimental results are provided to verify the effectiveness of the proposed bridgeless buck PFC rectifier. Copyright © 2016 John Wiley & Sons, Ltd.     

buck变换器的输出本质安全特性分析及优化设计

用buck变换器的电感和电容的最大储能之和反映其输出短路释放能量，推导了buck变换器在连续导电模式（CCM）和不连续导电模式（DCM）下的最大输出短路释放能量，若它们部小于最小点燃放电能量，则该变换器是满足输出本安要求的。指出如果变换器在最小负载电阻和最高输入电压的情况下处于CCM，则该状态下的输出短路能量就是该变换器在整个工作范围的最大输出短路释放能量。根据输出纹波电压指标将最小输出电容值用电感表示出来，并通过令最大输出短路释放能量对电感的偏导数为0的方法，得出在给定设计指标条件下使最大输出短路释放能量最小的电感和电容设计参数。实验结果验证了理论分析的正确性。     

High‐power‐factor single‐switch AC to DC converter for LED lighting

In this paper, we report a novel single‐switch AC to DC step‐down converter suitable for light emitting diodes. The proposed topology has a buck and a buck–boost converter. The circuit is designed to operate in the discontinuous conduction mode in order to improve the power factor. In this topology, a part of the input power is connected to the load directly. This feature of the proposed topology increases the efficiency of power conversion, improves the input power factor, produces less voltage stress on intermediate stages, and reduces the output voltage in the absence of a step‐down transformer. The theoretical analysis, design procedure, and performance of the proposed converter are verified by simulation and experiment. A 36 V, 60 W prototype has been built to demonstrate the merits of this circuit. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques is proposed in this article. The benefits of the accelerated pulse‐width‐modulation technique is fast‐transient response, simple‐compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage‐mode speed is slower with the transient response, so an accelerated pulse‐width‐modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm². Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley & Sons, Ltd.