共查询到20条相似文献，搜索用时 15 毫秒
1.
基于Matlab的调制解调系统仿真设计 总被引：6，自引：0，他引：6
设计了差分编码移相键控(2DPSK)调制解调系统的工作流程图,并利用Matlab软件对该系统的动态进行了模拟仿真。利用仿真的结果,从基带信号的眼图可以衡量数字信号的传输质量;由系统的输入和输出波形图可以看出,仿真实验良好。2DPSK调制解调系统的仿真设计,为以后进一步研究基于Matlab的通信实验仿真系统奠定了坚实的基础。 相似文献
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介绍了DDS技术的突出优点和DDS芯片ADT008频率合成的原理,在此基础上分析了用芯片AD7008进行数字调制的原理,并给出了实现4DPSK数字调制的方法． 相似文献
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Yuan Wang Shanliang Gan Song Jia Xing Zhang 《International Journal of Circuit Theory and Applications》2016,44(9):1758-1764
This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd. 相似文献
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Aravinda Koithyar T.K. Ramesh 《International Journal of Circuit Theory and Applications》2018,46(4):842-854
In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate–based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op‐amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage‐controlled oscillator is of conventional current–starved type. The divider makes use of true single‐phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage‐controlled oscillator. 相似文献
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介绍了由罗柯夫斯基线圈组成的电流互感器的基本原理 ,设计了一种通过VCO实现的V F转换电路。实验结果表明这种V F转换电路具有良好的实用性 相似文献
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针对高阶幅度相移键控(amplitude phase shift keying, APSK)解映射复杂度,不易硬件实现的问题,提出了一种低复杂度的APSK解映射方案及电路实现结构。具体而言,基于Max-Log-MAP算法,分析APSK星座图对称性并进行区域划分,对落到每个区域的接收符号比特软信息计算进行化简,得到具有低计算量的解映射公式。进一步,利用简化后每个比特软信息计算公式的特点,设计了软信息计算电路结构并在现场可编程门阵列(field programmable gate array, FPGA)硬件平台上进行了性能测试。测试结果表明,信噪比为14 dB时,利用简化方法实现的APSK解映射电路可实现10-5的误比特率(bit error rate,BER),与传统解映射算法性能接近,且具有较低的硬件资源消耗。 相似文献
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《International Journal of Circuit Theory and Applications》2017,45(8):1049-1059
We present a complete analysis of single and concurrent modes in fourth‐order LC‐voltage‐controlled oscillators ( VCOs), which are increasingly applied in dual‐band communication systems. We give a procedure based on the averaging method that simplifies the derivation of the abridged equations, which are derived without resorting to a change of co‐ordinates. The amplitudes of the oscillatory modes in steady state and in transient are found in explicit form. Conditions for the stability of the single and concurrent modes are derived, which apply to any active one‐port dual‐band LC‐VCO and allow one to predict the nonlinearities ensuring the occurrence of a stable concurrent mode. Numerical and experimental results show a good accuracy of the presented formulas. Copyright © 2016 John Wiley & Sons, Ltd. 相似文献
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Erik Pankratz Edgar Sánchez‐Sinencio 《International Journal of Circuit Theory and Applications》2014,42(9):871-938
This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
10.
本文首先对采用移相控制技术来抑制直流侧电压泵升时电网过电压倍数、负载功率因数、移相角及补偿电压大小之间的关系进行了理论分析,然后从能量平衡角度对直流侧电压泵升现象进行了讨论,揭示了直流侧电压变化与逆变器能量流动的关系,在此基础上提出了基于直流测电压闭环控制的移相控制策略,并给出了具体的实现方法。实验室3kW单相串联有源电压质量调节器以及容量分别为50kVA和100kVA的三相四线制串联有源电压质量调节器的实验结果表明,装置可以根据电网和负载运行状况自动对负载参考电压进行渐进移相,移相及直流侧电压泵升抑制效果非常好,对谐波、过压、不平衡等电压质量问题有良好的补偿作用,是一种实际可行的控制方法 相似文献
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Takashi Taya Akira Yoshida Nobusuke Yamaoka Shuichi Matsumoto Yoshikazu Yoshida 《Electrical Engineering in Japan》1998,125(2):35-43
In a large-scale broadband communication system, thousands of high-speed serial data interconnections are used and a bit synchronization circuit (a clock and data recovery circuit) is required in each of the receiver side interconnection circuits. In this paper, the requirements and the implementation of a bit synchronization circuit for the interconnection are considered, and one solution is proposed. In the proposed circuit, the oscillation phase of a VCO is directly controlled by the trigger signal extracted from the input data. Synchronization capture is quick and the circuit is applicable to burst signals. The circuit tolerates jitter and phase variation of the incoming data. The circuit requires no external components, and is suitable for an integrated circuit. The circuit was implemented using a 0.5 μm CMOS process and the data recovery operation from a 440 Mbps pseudo-random pattern was confirmed. Data acquisition is accomplished within three clock periods from 440 Mbps burst data. © 1998 Scripta Technica, Electr Eng Jpn, 125(2): 35–43, 1998 相似文献
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A. F. Abas B. Milivojevic A. Hidayat S. Bhandare D. Sandel H. Zhang R. Noé 《Electrical Engineering (Archiv fur Elektrotechnik)》2006,88(3):211-214
We report on transmission of a net aggregate data rate of 2.38 Tbit/s (excluding an assumed ~7% FEC overhead) over 273 km of fiber with just 16 100-GHz-spaced WDM channels. Due to polarization division multiplex and RZ-DQPSK modulation, each channel carries 160 Gbit/s (including the assumed FEC overhead) although the symbol rate is only 40 Gbaud. Polarizations are demultiplexed using automatic polarization control with a LiNbO3 polarization transformer. In-phase and quadrature data are demodulated in a 1-bit interferometer. 相似文献
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Meihong Liu Xingqun Zhan Wei Li Shuai Jing Maolin Chen 《IEEJ Transactions on Electrical and Electronic Engineering》2016,11(4):474-479
Because of the congestion of current navigation signals in the L band, the frequency band between 5010 and 5030 MHz allocated as C band with smaller ionospheric errors can be taken as a candidate band for global navigation satellite system (GNSS). The main objective of C band signal design is to achieve band limitation, compatibility, multipath resistance, satisfactory tracking, and acquisition performance. The minimum shift keying (MSK) chip waveform has been proven to be effective in providing better spectrum confinement and a constant envelope. However, the MSK chip waveform with an arbitrary binary coded symbol (BCS) may not meet the requirements of the C band. Thus, the BCS sequence ([s0,s1,⋯ ,sn − 1],fc) = ([1,1,1,1,−1,−1,1,−1,1,−1],1) is obtained by means of a thorough computer search for low autocorrelation side lobes based on a Neuman–Hofman code of length 10 with MSK pulses form MSK‐BCS ([1,1,1,1,−1,−1,1,−1,1,−1],1). It is proved to have better autocorrelation with a sharp main lobe and smaller side lobes, larger Gabor bandwidth, smaller Cramér–Rao lower bound, and less multipath error; more importantly, it can satisfy the threshold of leakage out of band. It will be of great significance for signal design in C band. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. 相似文献
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Madhab Chandra Tripathy Debasmita Mondal Karabi Biswas Siddhartha Sen 《International Journal of Circuit Theory and Applications》2015,43(6):776-792
The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd. 相似文献
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基于单相锁相环的高压直流分相触发相位控制 总被引：1，自引：1，他引：1
触发相位控制是高压直流系统控制的基础。换流器触发相位控制方式对高压直流性能的影响尤以不对称故障工况下为甚。针对传统分相触发中过零点检测抗干扰性差以及等间隔触发控制自由度低等缺点,提出一种新的基于单相锁相环的分相触发方案,该触发方式的锁相过程对谐波和负序电压干扰具有较强的抑制能力,能够在三相不对称工况下获得更详细的电压相位信息,减小此时各阀实际触发角的差异。最后,利用PSCAD/EMTDC对所提分相触发方式下高压直流稳态和暂态性能进行了仿真测试和分析,结果表明新分相触发对系统稳态性能无不利影响,并可有效降低交流故障恢复过程发生后续换相失败的概率,验证了该分相触发方式的优越性。 相似文献
17.
Athanasios Tsitouras Fotis Plessas Grigorios Kalivas 《International Journal of Circuit Theory and Applications》2011,39(8):823-833
A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125°C). Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
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Kulbhushan Sharma;Ayush Kumar;Jaya Madan;Rahul Pandey; 《International Journal of Numerical Modelling》2024,37(2):e3212
Low-noise and low-voltage operation is prime requirement of an operational transconductance amplifier for low frequency applications. However, achieving low-noise operation at low supply voltages is a challenging task in CMOS technology owing to noise-power and noise-stability tradeoffs. This article outlines, the design of four differential bias self-cascode (DBSC) operational transconductance amplifiers (OTAs) working at ±0.7 V. The four design techniques namely gate driven (GD), bulk driven (BD), bulk driven quasi-floating gate (BDQFG), and gate driven quasi floating bulk (GDQFB) have been applied on DBSC OTAs. The designing aspects and performance parameters of these four OTAs such as gain, gain-bandwidth, input referred noise (IRN), settling time (ST), common mode rejection ratio (CMRR), total harmonic distortion, input impedance, transconductance, power consumption, area consumption and process/mismatch variations have been fairly compared in this work. These DBSC OTAs have been designed and simulated using a standard 0.18-μm 6M1P CMOS N-well process. The results infer GD DBSC OTA shows high CMRR of 125.83 dB. While the BD DBSC OTA consumes very low power of 0.2 μW. The BDQFG DBSC OTA shows low 1% ST of 24.83 μS. The GDQFB DBSC OTA show high transconductance (2.35 mS), high gain (64.97 dB), and low IRN (0.40 μV/√Hz at 10 Hz). The theoretical predictions for these OTAs agree with the post-layout simulations. The proposed OTAs can be used for designing various analog circuits such as programmable gain amplifiers, variable gain amplifiers, and transimpedance amplifiers for low-frequency biomedical and health care applications. 相似文献
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定义了区内故障穿越电流。对穿越电流的研究显示,传统稳态量差动保护区内故障时的保护灵敏度受负荷电流影响大,带过渡电阻能力与故障点位置相关。通过在制动特性中引入穿越电流,提出了一种改进的稳态量电流差动判据。理论分析表明:改进判据与传统稳态量差动保护判据区外故障的安全性完全相同,但改进判据在区内故障的灵敏度以及带过渡电阻能力大大提高了。对一条750kV线路故障和保护的仿真试验,证明了改进判据的上述优越性,是一种比较理想的超特高压输电线路电流差动保护判据。 相似文献