用DDS实现的4DPSK调制器

介绍了DDS技术的突出优点和DDS芯片ADT008频率合成的原理，在此基础上分析了用芯片AD7008进行数字调制的原理，并给出了实现4DPSK数字调制的方法．     

基于Matlab的调制解调系统仿真设计

设计了差分编码移相键控(2DPSK)调制解调系统的工作流程图,并利用Matlab软件对该系统的动态进行了模拟仿真。利用仿真的结果,从基带信号的眼图可以衡量数字信号的传输质量;由系统的输入和输出波形图可以看出,仿真实验良好。2DPSK调制解调系统的仿真设计,为以后进一步研究基于Matlab的通信实验仿真系统奠定了坚实的基础。     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate–based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op‐amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage‐controlled oscillator is of conventional current–starved type. The divider makes use of true single‐phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage‐controlled oscillator.     

一种用在Rogowski线圈电流互感器中的V/F转换电路的设计

介绍了由罗柯夫斯基线圈组成的电流互感器的基本原理 ,设计了一种通过VCO实现的V F转换电路。实验结果表明这种V F转换电路具有良好的实用性     

低复杂度高阶APSK解映射方法与实现结构

针对高阶幅度相移键控(amplitude phase shift keying, APSK)解映射复杂度,不易硬件实现的问题,提出了一种低复杂度的APSK解映射方案及电路实现结构。具体而言,基于Max-Log-MAP算法,分析APSK星座图对称性并进行区域划分,对落到每个区域的接收符号比特软信息计算进行化简,得到具有低计算量的解映射公式。进一步,利用简化后每个比特软信息计算公式的特点,设计了软信息计算电路结构并在现场可编程门阵列(field programmable gate array, FPGA)硬件平台上进行了性能测试。测试结果表明,信噪比为14 dB时,利用简化方法实现的APSK解映射电路可实现10^-5的误比特率(bit error rate,BER),与传统解映射算法性能接近,且具有较低的硬件资源消耗。     

移相控制技术在串联有源电压质量调节器中的应用

本文首先对采用移相控制技术来抑制直流侧电压泵升时电网过电压倍数、负载功率因数、移相角及补偿电压大小之间的关系进行了理论分析，然后从能量平衡角度对直流侧电压泵升现象进行了讨论，揭示了直流侧电压变化与逆变器能量流动的关系，在此基础上提出了基于直流测电压闭环控制的移相控制策略，并给出了具体的实现方法。实验室3kW单相串联有源电压质量调节器以及容量分别为50kVA和100kVA的三相四线制串联有源电压质量调节器的实验结果表明，装置可以根据电网和负载运行状况自动对负载参考电压进行渐进移相，移相及直流侧电压泵升抑制效果非常好，对谐波、过压、不平衡等电压质量问题有良好的补偿作用，是一种实际可行的控制方法     

A large dynamic range voltage controlled attenuator with improved linearity-in-dB for ultrasound applications

A large dynamic range (DR) and high linearity-in-dB voltage controlled attenuator (VCAT) for ultrasound applications was presented. Continuous tunable VCAT implemented with Metal-Oxide-Semiconductor (MOS) transistors used as shunt devices was proposed in this work, and the linearity-in-dB performance was analyzed in detail. Nonlinearity of the shunt transistors operated in different regions resulted in poor linearity-in-dB attenuation of the VCAT, which was undesirable in an ultrasonic receiver system. An effective linearity-in-dB improvement scheme was then proposed. The full scale range of the input control voltage was divided into N intervals with a same equal-length by uniformly distributed voltage values. At these division voltages, the attenuation gains were corrected to be the ideal ones by the tracing and comparing circuits. In this way, the non-linearity-in-dB was limited to the intervals between the two adjacent corrected attenuation gains, and the overall linearity of the VCAT was improved greatly. Measurement results showed that the dynamic range of the proposed attenuator was 36-dB, and the gain errors were in a range from − 1.22 to − 0.55 dB. The noise figures (NF) at the commonly used ultrasonic frequencies was below 6-dB, and the S11 was better than − 10 dB over the input range of the control voltage.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.