A symmetric quantum-dot cellular automata design for 5-input majority gate

By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

Monte-Carlo Simulation of Clocked and Non-Clocked QCA Architectures

We present a Monte Carlo simulation of two implementations of Quantum Cellular Automaton (QCA) circuits: one based on simple ground state relaxation and the other on the clocked cell scheme that has recently been proposed by Tóth and Lent. We focus on the time-dependent behavior of two basic circuits, a binary wire and a majority voting gate, and assess their maximum operating speed and temperature requirements for different sets of fabrication parameters.     

Design of a reversible structure for memory in quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) technology has limitations in reducing the area and size of circuits. The disadvantages of this technology include high power consumption and temperature problems. Quantum-dot cellular automata (QCA) is a new technology that can overcome these shortcomings. Reversible logic is technology used to reduce the power loss in QCA. QCA can be used to design memories that require high operating speed. In this paper, we propose a structure for the reversible memory in QCA. The proposed structure utilizes three-layer technology, which has a significant impact on circuit size reduction. The proposed structure for the reversible memory has 63% improvement in cell number, a 75% improvement in area occupancy, and a 60% reduction in delay compared to the previous best structure.     

A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology

Quantum dot cellular automata (QCA) with the characteristics such as low energy dissipation and high density is a suitable alternative technology to CMOS technology. Arithmetic logic unit (ALU) is one of the most important critical components of a microprocessor, and it is the core component of central processing unit (CPU). In this work, a novel reversible ALU in QCA nanotechnology is proposed. The reversible ALU contains three Ferdkin gates and one HNG gate. The proposed structure needs one constant input and generates only one garbage output. The proposed circuit does not need any rotated cells and only uses one layer that improves the manufacturability of the design interestingly. This circuit can perform 20 operations such as AND, OR, XOR, XNOR, COPY, addition, and increment. Our design contains only 480 cells and 12 majority voters and requires 15 clock phases. The proposed structures are simulated using QCADesigner version 2.0.3. The reversible ALU, despite a 25% increase in operations, has a 28% improvement in cell numbers and a 6% improvement in delay.     

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of \(0.02\,\upmu \hbox {m}^{2}\) and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.     

A novel QCA implementation of MUX-based universal shift register

QCA (Quantum-dot Cellular Automata) is an alternative technology for CMOS that has a low power consumption and high density. QCA extensively supports the new plans in the field of nanotechnology. Applications of QCA technology as an alternative method for CMOS technology in nano-scale have a hopeful future. This paper presents the successful design, implementation and simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexer with the minimum area as compared to the previous models in QCA technology. In this paper, by means of 4 to 1 multiplexers including D-Flip Flop (D-FF) structure in QCA, we present an 8-bit universal shift register. The structure of the 8-bit universal register is extendable to 16-bit, 32-bit and etc. In this paper, the successful simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexers, including D-FF and finally 8-bit universal register structure in QCADesigner is provided. The multiplexers and D-FF presented in this paper have the minimum complexity, area and delay compared to the previous models. In this paper, the implementation of 8-bit universal shift register, by means of 4 to 1 multiplexers and D-FF are presented in QCA technique which have the minimum complexity and delay. In the proposed design of the 8-bit universal shift register, the faults are likely to occur at 2 to 1 multiplexers and D-FF. In this article, 2 to 1 multiplexers and D-FF are investigated from the cell missing and possible defects. Considering the pipeline being the virtue of QCA, the 8-bit universal shift register has a high speed function. This 8-bit universal shift register may be used in the high speed processors as well as cryptography circuits.     

New approaches for modeling and simulation of quantum-dot cellular automata

In order to further development of the microelectronic systems and to achieve the circuits with higher speed, higher density and lower power consumption, new technologies to replace the conventional CMOS technology must be introduced. Quantum-dot cellular automata (QCA) is an emerging nanotechnology that provides a new method for computation at the nanoscale regime. In this paper, two methods e.g. artificial neural network and a mathematical algorithm based on the QCA cell–cell response function named Tansig method are used for the modeling and simulation of QCA circuits at the cell level. The accuracy and performance of the proposed methods are analyzed through few circuits. The results of these two approaches are compared with each other and QCADesigner software. The results show the feasibility and acceptable accuracy of these types of simulations. Also, these methods enable the simulation of large QCA circuits at the cell level with acceptable precision in a short time with the ability to implement in other circuit simulators such as HSPICE and so on.     

Towards the design of hybrid QCA tiles targeting high fault tolerance

The increasing fabrication cost of CMOS-based computing devices and the ever-approaching limits of their fabrication have led to the search for feasible options with high device density and low power waste. Quantum-dot cellular automata (QCA) is an emerging technology with such potential to match the design target beyond the limits of state-of-the-art CMOS. But nanotechnologies, like QCA are extremely susceptible to various forms of flaws and variations during fabrication at nano scale. Thus, the exploration of ingenious fault tolerant structure around QCA is gaining high importance. This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy. Different QCA logic primitives (majority/minority logic, fanout tiles, etc.) are made using such hybrid cell structure. The functional characterization using the kink energy and the polarization level of such QCA structures under different cell defects have been thoroughly investigated. The results suggest that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %. Also, 100 % fault tolerance can be ascertained if the proposed logic circuit drives the correct output with the application of \(\langle \)001, 011\(\rangle \) as a primitive test vector only. A comparative performance of the proposed logic over existing structure makes it more reliable.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis of field-driven clocking for molecular quantum-dot cellular automata based circuits

Molecular quantum-dot cellular automaton (QCA) offers an alternative paradigm for computing at the nano-scale. QCA circuits require an external clock which can be generated using a network of submerged electrodes to synchronize information flow and provide the required power to drive the computation. In this paper, the effect of electrode separation and applied potential on the likelihood of different QCA cell states of molecular cells located above and in between two adjacent electrodes is analyzed. Using this analysis, estimates of operational ranges are developed for the placement, applied potential, and relative phase between adjacent clocking electrodes to ensure that only those states that are used in the computation are energetically favorable. Conclusions on the trade-off between cell size, cell-to-cell distance, and applied clocking potential are drawn and the temperature dependence of the operation of fundamental QCA building blocks is considered.     

Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

Scaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits. Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.     

一种缓解NBTI效应引起电路老化的门替换方法

45 nm工艺下,负偏置温度不稳定性（negative bias temperature instability,NBTI）效应是限制电路的性能的首要因素。为了缓解NBTI效应引起的电路老化,提出了1个基于门替换方法的设计流程框架和门替换算法。首先利用已有的电路老化分析框架来预测集成电路在其服务生命期内的最大老化,然后以门的权值作为指标来识别关键门,最后采用门替换算法对电路中的部分门进行替换。基于ISCAS85基准电路和45 nm晶体管工艺的试验结果表明,相对于已有的方法,采用文中的门替换方法,使得NBTI效应引起的电路老化程度平均被缓解了9.11%,有效地解决了控制输入向量（input vector control,IVC）方法不适用于大电路问题。     

QCA技术在递归盒式滤波器中的应用

量子点元胞自动机(quantum dot-cellular automata, QCA)因其延迟时间短、功耗低以及占用面积小等优点被当作代替CMOS的新型技术之一。针对CMOS器件尺寸日益减小导致的高功耗和电容寄生及串扰问题,本文首次利用QCA技术构建了一种递归盒式滤波器。其中,提出了一种全新的QCA全加器,较已提出的QCA全加器减少了55%的电路面积;少使用了56.7%的元胞数;量子成本也降低了10%以上。并以此为基础设计了一种高效的行波进位加法器(ripple carry adder, RCA)以及一种高效的进位选择加法器(carry select adder, CSA)来构成盒式滤波器的加法单元。以此构建的盒式滤波器较一般QCA盒式滤波器节省了32.6%的硬件资源;减少20%的电路运行时间;减少了48.7%的功耗。并使用QCA Designer仿真,结果表明,本设计完全可以代替实现传统的盒式滤波器功能,并在效率、功耗、电路面积、资源占用方面均有显著降低。     

Calculating the steady-state polarizations of quantum cellular automata (QCA) circuits

We present on the use of well-known stochastic methods for computing the steady-state polarizations of quantum cellular automata (QCA) circuits. Typically, a Boltzmann distribution, which requires the exploration of the complete configuration space of an \(N\) -cell QCA circuit, is used to compute the \(2^N\) steady-states of the QCA circuit. However, the exponential growth in states as the circuit size grows makes computing the Boltzmann distribution infeasible for large circuits. Thus, we approximate the Boltzmann distribution of a QCA circuit by conducting a partial exploration of the complete configuration space by means of a Monte Carlo method, simulated annealing, and a genetic algorithm. The approximated Boltzmann distribution from each method was able to compute the steady-state polarizations with a very high degree of accuracy, with the simulated annealing algorithm producing the best results.     

Power·delay product in COSMOS logic circuits

In this simulation work, we use COSMOS logic devices—a novel single gate CMOS architecture recently announced [1]—in multi-input logic gates, assessing its performance in terms of power·delay product. We consider three different multi-input logic circuits: a two-input NOR gate, a three-input NOR gate, and a three-input composite NOR/NAND (NORAND) gate. For this power·delay analysis, the transient TCAD simulations are employed in a mixed-mode approach where circuit and device simulations are coupled together, culminating in the delay response of the circuits as well as the static/dynamic current components. The analysis shows that all circuits, except the 3-input NOR gate, has acceptable characteristics at low-power applications and static leakage limits all COSMOS circuits at high-bias conditions.     

A novel quantum-dot cellular automata CLB of FPGA

Quantum-dot cellular automata (QCA) is a promising, emerging nano-technology based on single electron effects in quantum dots and molecules. This paper presents design, implementation and simulation of a configurable logic block for a field programmable gate arrays (FPGA) by QCA. Previous works focus on QCA-based FPGA that have fixed logic and programmable interconnection or programmable logic and fixed interconnection; however, proposed structures in this paper have programmable logic and programmable interconnection. The presented look-up table implemented with novel structure which has been allowed as frequently as the read/write operation occurs, also acts as a pipeline. In this paper, we presented novel decoders and multiplexers and implemented with QCA, designed with the minimum number of majority gates and cells. Finally, a new configurable logic block (CLB) is designed, implemented and simulated in the QCA, which used signal distribution network method to avoid the coplanar problem of crossing wires. Also, QCADesigner software is used for detailed layout and QCADesigner attend with HDLQ verilog are used for circuit simulation. The proposed CLB is simulated with programming by the QCADesigner software. The area and delay of QCA-based CLB presented in this paper compared to the CLB based on CMOS, nanomaterial and CNT (32 nm). Results show that proposed CLB will do the task with a minimum clock and can be configured as a FPGA.     

Asymmetric transistor sizing targeting radiation-hardened circuits

This article proposes a technique to improve the dependability of circuits under energetic particle irradiation by resizing transistors in the most critical paths. First, the SET vulnerability of a mapped circuit is analyzed to identify the most sensitive nodes. The sensitivity of the circuit is defined by the logical and electrical masking. Once the most critical nodes are selected, a transistor sizing algorithm is able to resize the pull-up and pull-down transistors separately. The asymmetric resizing offers interesting area and performance trade-off in comparison with gate sizing and gate duplication techniques. Results show very small area and performance penalties for circuits operating at ground level for a 130-nm technology process.