A 15-MHz bandwidth double sampling MASH25b-15b sigma-delta modulator with DEM for multibit DACs

A high SNDR discrete-time (DT) 2-1 MASH sigma-delta modulator (SDM) for 15-MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five-bit flash quantizer was adopted in both stages to improve the overall signal-to-noise and distortion ratio (SNDR) performance, and third-order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18-μm CMOS technology, the occupied area of the modulator was 0.24 mm² and dissipation power 25.4 mW from a 1.8-V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15-MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious-free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5-dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15-MHz bandwidth. A 15-MHz bandwidth multibit MASH2-1 discrete-time sigma-delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High-order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18-μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15-MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high-frequency biomedical imaging or sensing systems, and so on.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

A study of a low-voltage,low-power,current-mode Σ Δ modulator circuit

The possibility of realizing a low-voltage and low-power audio-band Σ Δ modulator has been studied. The current-mode circuit technique has been adopted to enable the modulator to operate at less than 3 V supply voltage. The modulator to uses analog integrators instead of switched-capacitor-type integrators to avoid the use of analog switches, which allows low-voltage operation of the modulator circuit. A newly designed voltage-to-current converter is used to form an analog integrator. The designed circuit was actually fabricated by using a CMOS 0.6 μm process and its characteristics were evaluated. A signal-to-noise ratio of 68 dB in a 20 kHz bandwidth for the first-order modulator construction was measured from the 2.5 V supply voltage at an oversampling ratio of 256. However, only 72 dB of the signal-to-noise ratio and 65 dB of distortion were measured for the second-order modulator construction, although operation of the oversampling ratio of 48 was successfully confirmed. We concluded that low-voltage and low-power operation with less than 3 V of supply voltage is possible for the audio-band Σ Δ modulator, although signal-to-noise ratio and distortion issues in the 2nd-order configuration are left for future study. © 1998 Scripta Technica, Electr Eng Jpn, 124(1): 24–32, 1998     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

A terabit-per-second all-optical four-bit digital-to-analog converter using quantum dot semiconductor optical amplifiers

An all-optical digital-to-analog converter (DAC) using quantum dot semiconductor optical amplifiers (QDSOAs) is proposed and analyzed. The device operates at low optical power (~?0.5 mW) at a speed of 1 Tbps. The resolution of the DAC is four bits, and the corresponding step size is 1.068 mW (compared with the ideal value of 1 mW). The dynamic range is found to be 11.47 dB (versus the ideal value of 11.76 dB). The average absolute error for all the states of the proposed optical DAC is 0.53%, with a maximum error of 1.85%, being the first time that such performance has been achieved to the best of the authors’ knowledge. It is shown that the amplified spontaneous emission (ASE) noise has no significant effect on the performance of the DAC.

     

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

In this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <?61‐dB IMD with 1.25‐GHz sampling frequency.     

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a 0.18‐μm CMOS technology. Theoretical analyses and circuit simulations show 30% and 65% reduction in 3‐dB bandwidth of the SR receiver at 25 Mbps data rate by employing the proposed quench signal compared with piecewise‐linear and trapezoidal quench waveforms, respectively. Performance of the proposed front‐end is evaluated by a fast bit‐error‐rate estimation procedure, based on circuit noise simulations and statistical analyses, without the need for time‐consuming transient‐noise simulations. Accuracy of the procedure has been verified by comparing its results with transient‐noise simulations. According to the estimated bit‐error‐rate curves, the noise‐canceling topology with S2D converter enhances the SR receiver sensitivity by 9 dB. Copyright © 2017 John Wiley & Sons, Ltd.     

Variation‐aware widely tunable nanoscale design of CMOS active inductor‐based RF bandpass filter

This paper presents a novel design methodology for realizing a variation‐aware widely tunable active inductor‐based RF bandpass filter (BPF). The inductor‐less filter is designed and implemented using voltage differencing transconductance amplifier (VDTA) as an active building block and a grounded capacitor, thereby validating its suitability for fully integrated circuit applications. Digital ‘coarse’ tuning and analog ‘fine’ tuning are employed to achieve better frequency coverage. The designed filter exhibits a tuning range of 1.65–3.015 GHz and a 3‐dB bandwidth of 1400–122 MHz which translates into a quality factor of 1.17–24.71. It offers a voltage gain of 0–22.91 dB, noise figure of 28.16–28.95 dB, has a 1‐dB compression point of 2.50–2.478 dBm and draws 0.065–0.232 mW power from 1‐V power supply. Our proposed design shows a figure‐of‐merit of 82.08–91.27 dB, which is higher as compared to its counterparts available in the literature. The filter is implemented in 45‐nm CMOS technology node using metal gate and strained silicon. Copyright © 2017 John Wiley & Sons, Ltd.     

Compact memristor-based ultra-wide band chirp pulse generator

In this letter, a memristor-based chirp pulse generator circuit is introduced for ultra-wideband transceivers for the first time. The proposed generator is built using memristor-controlled ring oscillator. Memristor is used to replace the bulky components in the chirp pulse generation such as surface acoustic wave filters and reactive components (capacitor and inductors), which reflects a huge reduction in area and power. The chirp pulse frequency of the proposed circuit varies linearly with time over the pulse duration due to the change in the memristance. The proposed circuit is mathematically analyzed and designed using 65-nm complementary metal-oxide-semiconductor (CMOS) technology. The 500-MHz bandwidth is demonstrated using a 32-ns pulse width complying with the FCC regulations. The power consumption is 84 μW with a 10-MHz pulse repetition frequency (PRF).     

低复杂度高阶APSK解映射方法与实现结构

针对高阶幅度相移键控(amplitude phase shift keying, APSK)解映射复杂度,不易硬件实现的问题,提出了一种低复杂度的APSK解映射方案及电路实现结构。具体而言,基于Max-Log-MAP算法,分析APSK星座图对称性并进行区域划分,对落到每个区域的接收符号比特软信息计算进行化简,得到具有低计算量的解映射公式。进一步,利用简化后每个比特软信息计算公式的特点,设计了软信息计算电路结构并在现场可编程门阵列(field programmable gate array, FPGA)硬件平台上进行了性能测试。测试结果表明,信噪比为14 dB时,利用简化方法实现的APSK解映射电路可实现10^-5的误比特率(bit error rate,BER),与传统解映射算法性能接近,且具有较低的硬件资源消耗。     

A mathematical method to realize complex poles in a high-order passive switched-capacitor filter

A high-order discrete-time IIR low-pass with complex poles using charge sampling is presented in a single-stage structure by using a mathematical strategy. In comparison with the analog complex-poles G_m-C filters, the proposed filter consumes lower power and has good linearity, and all of the tunings are implemented only by capacitor sizes. The proposed filter is a seventh-order Butterworth, but this method can be generalized to implement other complex pole filters like Tchebyshev and Elliptic. Post-layout simulation results in 130-nm complementary metal-oxide-semiconductor (CMOS) show an IIP3 of +18 dBm and a noise figure of 5 dB. The filter has a rejection of more than 110 dB in its stop band and consumes 1.5 mW with a 1.6-V supply voltage, and circuit occupies an about 0.12 mm² of silicon.     

Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area

In this paper, a switching scheme is presented to reduce the capacitive digital-to-analog converter (DAC) switching energy, area, and the number of switches in successive approximation register (SAR) analog-to-digital converters (ADCs). In the proposed DAC switching method, after a few most significant bits (MSBs) decision, the sampled differential input signal is shifted into two special regions where the required DAC switching energy and area is less than the other regions. This technique can be utilized in most of the previously reported DAC switching schemes to further reduce the capacitive DAC switching energy and area. The conventional and two recently presented DAC switching techniques are utilized in the proposed SAR ADC to evaluate its usefulness.     

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.     

Newly proposed hybrid resonant commutation bridge‐leg link snubber‐assisted three‐phase ZVZCS‐PWM soft‐switching inverter

This paper presents the newly proposed hybrid resonant commutation bridge‐leg link (HRCB) snubber circuit which can achieve zero voltage and zero current soft‐switching commutation for single‐phase and three‐phase voltage source‐type inverter, along with its unique features and operation principle. The circuit parameter design approach for the HRCB snubber circuit and the determination estimating scheme of the gate pulse timing processing which is more suitable and acceptable for single‐phase and space voltage vector modulated three‐phase voltage source inverter using the HRCB snubber circuit are described in this paper. In particular, the three‐phase voltage source soft‐switching inverter associated with the proposed HRCB circuits are evaluated and discussed from simulation and experimental viewpoints. The practical effectiveness of the HRCB snubber‐assisted three‐phase voltage source soft‐switching inverter using IGBT power modules which is based on the instantaneous space voltage vector modulation is clarified on the output voltage waveform, actual efficiency of electromagnetic noise in comparison with three‐phase voltage source‐type conventional hard‐switching inverter. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(4): 75–84, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20111     

Run-time calibration scheme for the implementation of a robust field-programmable gate array–based time-to-digital converter

In this study, we propose a robust field-programmable gate array (FPGA)–based time-to-digital converter (TDC) with run-time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four-step finite state machine (FSM) for run-time calibration. We implemented the TDC with the proposed run-time calibration circuit on the Xilinx 65-nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run-time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27°C to approximately 70°C indicated that the proposed run-time calibration circuit enhanced the capability of the FPGA-based TDC against temperature effects. The FPGA-based TDC with the proposed run-time calibration FSM provides robust high-resolution performance suited for a range of scientific applications.     

A novel active auxiliary circuit for efficiency enhancement integrated with synchronous buck converter

In this paper, a novel auxiliary circuit is introduced for the synchronous buck converter. This auxiliary circuit provides zero‐current, zero‐voltage switching conditions for the main and synchronous switches while providing zero‐current condition for the auxiliary switch and diodes. The proposed active auxiliary circuit integrated with synchronous buck converter that emanates to zero‐voltage transition (ZVT)–zero‐current transition (ZCT) pulse width‐modulated (PWM) synchronous buck converter is analyzed, and its operating modes are presented. The additional voltage and current stresses on main, synchronous and auxiliary switches get decimated because of the resonance of the auxiliary circuit that acts for a small segment of time in the proposed converter. The important design feature of soft‐switching converters is the placement of resonant components that mollifies the switching and conduction losses. With the advent of ZVT–ZCT switching, there is an increase in the switching frequency that declines the resonant component values in the converters and also constricts the switching losses. The characteristics of the proposed converter are verified with the simulation in the Power Sim (PSIM) software co‐simulated with MATLAB/SIMULINK environment and implemented experimentally. Copyright © 2016 John Wiley & Sons, Ltd.     

Temperature‐dependent modeling and performance analysis of coupled MLGNR interconnects

The temperature‐dependent circuit modeling and performance in terms of propagation delay, power dissipation, and crosstalk‐induced voltage waveform at the far end of victim line of multilayer graphene nanoribbon (MLGNR) interconnects have been analyzed at 22 nm technology node. A comparative performance analysis between MLGNR interconnects with resistance estimated using temperature‐dependent model and temperature‐independent model is examined. The results obtained are also compared with capacitively coupled interconnects of copper (Cu). The results show that as the temperature is varied from 300 K to 500 K, MLGNR has lower propagation delay and power dissipation as compared to Cu for 1 mm long interconnects. It is also observed that because of the dominance of both low resistance and ground capacitance compared to Cu, MLGNR has better crosstalk‐induced delay and voltage waveforms with rise in temperature at the far end of aggressor and victim line, respectively. Further, simulated results show an average relative improvement in propagation delay of 37.24% and corresponding improvement in power dissipation of approximately 19.59% by using a temperature‐dependent model in comparison to a temperature‐independent model of MLGNR resistance with interconnect lengths varying from 200 to 1000 μm. The reduction in the time duration of victim output pulse over these interconnect lengths also shows a significant improvement of approximately 35% by using temperature‐dependent model as against temperature‐independent model of MLGNR resistance.     

A direct conversion transmitter with digital‐assisted DC offset and I/Q phase calibration

A direct conversion transmitter with auto‐calibration mechanism is presented in this paper. Both the carrier leakage and in‐phase/quadrature (I/Q) phase imbalance are compensated by a proposed calibration algorithm to improve transmitter's single‐sideband performance. The digital‐assisted correction circuits are implemented in a calibration feedback path to reduce the mismatches and variations, which in turn achieves properties of high linearity, high sideband, and carrier suppression ratio. The measured single‐sideband performance with calibration applied to the transmitter demonstrates an over 40 and 50‐dBc rejection on sideband and carrier signals at the desired frequency band, respectively. For linearity performance, the measured output 1‐dB compression point (OP1dB) is 9.1 dBm, while the highest voltage gain is from 4.3 to 6.2 dB. Additionally, the error vector magnitude (EVM) of −37.082 dB (< 1.4%) can be achieved under an orthogonal frequency division multiple access (OFDMA) 64 QAM‐3/4 modulated signal test. The transmitter consumes 112.7 mA under supply voltage of 3.3 V using the TSMC SiGe BiCMOS technology. Copyright © 2017 John Wiley & Sons, Ltd.     

准循环LDPC码在电力线通信中的仿真应用

文章将电力线信道建模为加性白色A类噪声信道,在该信道模型中采用改进BP译码算法,研究准循环LDPC码的抗脉冲噪声性能,给出了在不同迭代次数下的仿真结果(表现出不同的译码性能)。仿真试验证明:采用改进的BP译码算法,当信噪比在4.6 dB时,比特误码率达10-5,可以满足实际应用的需要。本研究为准循环LDPC码在PLC中的应用提供了理论与实验依据。