An optimization based design for integrated dependable real-time embedded systems

Moving from the traditional federated design paradigm, integration of mixed-criticality software components onto common computing platforms is increasingly being adopted by automotive, avionics and the control industry. This method faces new challenges such as the integration of varied functionalities (dependability, responsiveness, power consumption, etc.) under platform resource constraints and the prevention of error propagation. Based on model driven architecture and platform based design’s principles, we present a systematic mapping process for such integration adhering a transformation based design methodology. Our aim is to convert/transform initial platform independent application specifications into post integration platform specific models. In this paper, a heuristic based resource allocation approach is depicted for the consolidated mapping of safety critical and non-safety critical applications onto a common computing platform meeting particularly dependability/fault-tolerance and real-time requirements. We develop a supporting tool suite for the proposed framework, where VIATRA (VIsual Automated model TRAnsformations) is used as a transformation tool at different design steps. We validate the process and provide experimental results to show the effectiveness, performance and robustness of the approach.     

A highly flexible sea-of-gates structure for digital and analogapplications

A sea-of-gates structure optimized for digital random logic applications as well as for regular arrays and analog circuits is described. Associated with a dedicated design procedure and a systematic metallization strategy, the structure features a full cell-abutment capability and true channelless routing. After reviewing the advantages and limitations of currently available arrays, the main characteristics of the array architecture are presented, and applications to different circuit families are detailed. Design automation tools suited to the structure and design methodology are reviewed. Design results and performance are presented for several macroblocks and are compared with other semicustom approaches. A set of rules which allows an automatic transformation of the sea-of-gates layout into a topologically equivalent full-custom layout, converting semicustom prototypes to full-performance circuits, is presented     

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-mum CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution (<12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.     

Synthesis of area-efficient and high-throughput rate data formatconverters

This paper proposes two design methodologies for synthesis of area-efficient data format converters (DFCs) with high throughput rate. DFCs are grouped into various classes according to the specification of design parameters. The first design methodology is suitable for design of many representative classes of DFCs. The designs using this methodology are based on a two-dimensional (2-D) architecture. They have maximum throughput rate and are area-efficient. Various design examples are shown to demonstrate improved performance, flexibility and usefulness of this design methodology. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, this methodology leads to compact designs. The second design methodology employs an architecture using dual buffers. The simple and regular architecture using dual buffers leads to area-efficient DFCs. The design procedure using this methodology is simple and can reduce the design effort in many applications     

Statistical computer-aided design for microwave circuits

A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making “designing for circuit manufacturability” a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology     

Noise–Power Optimization of Incremental Data Converters

Incremental data converters (IDCs) are useful in instrumentation and measurement applications, where low-frequency analog signals need to be converted into digital form with high accuracy and low power dissipation. They are particularly well suited for applications where a single analog-digital converter is multiplexed between many channels. This paper proposes an exact design methodology for IDCs, which optimizes the signal-to-noise ratio of the converter under practical design constraints. The process also allows the designer to apportion the noise budget in an arbitrary manner between thermal and quantization noise. The design process is illustrated by an example which describes the optimization of a third-order multiplexed IDC.     

Sensor-based design of a Delta parallel robot

This paper proposes a sensor-based design methodology in order to design a Delta robot with guaranteed accuracy performance for a dedicated sensor-based controller. This sensor-based design methodology takes into account the accuracy performance of the controller in the design process in order to find optimal geometric parameters of the robot. Three types of controllers are envisaged to be applied to the Delta robot, leading to three different optimal designs: leg-direction-based visual servoing, line-based visual servoing and image moment visual servoing. Based on these three controllers, positioning error models taking into account the error of observation coming from the camera are developed, and the controller singularities are analyzed. Then, design optimization problems are formulated in order to find the optimal geometric parameters and relevant parameters of the camera for the Delta robot for each type of controller. Prototypes of Delta robots have been manufactured based on the obtained optimum design parameters in order to test the performance of the pair {robot-controller}.     

Efficient exploration of bus-based system-on-chip architectures

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.     

Statistical methods for the estimation of process variation effects on circuit operation

In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits.     

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI

Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.     

Developing a linear piezomotor with nanometer resolution and high stiffness

A novel linear piezomotor was developed for machine tool applications. The design principles and methodology for this high stiffness linear piezomotor with nanometer resolution are presented. The linear piezomotor consists of three piezoelectric actuators and one monolithic flexure frame. The design strategy is to reduce the total number of mechanical elements and interfaces and to integrate all the elements into the frame. The finite element method is used in the design process. The principles and methodology are also applicable to other positioning systems where a high stiffness and high positioning resolution are required.     

System-level power-performance tradeoffs for reconfigurable computing

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.     

A framework for reconfigurable computing: task scheduling andcontext management

Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations     

A holistic concurrent design approach to robotics using hardware-in-the-loop simulation

This paper discusses a practical approach to the concurrent design of robot manipulators, which is based on an alternative design methodology, namely Holistic Concurrent Design (HCD), as well as the utilization of a modular hardware-in-the-loop simulation. Holistic concurrent design is a systematic design methodology for mechatronic systems that formalizes subjective notions of design, resulting in the simplification of the multi-objective constrained optimization process. Its premise is to enhance the communication between designers with various backgrounds and customers, and to consider numerous design variables with different natures concurrently. The methodology redefines the ultimate goal of design based on the qualitative notion of satisfaction, and formalizes the effect of designer’s subjective attitude in the process. The hardware-in-the-loop platform involves physical joint modules and the control unit of a manipulator in addition to the software simulation to reduce modeling complexities and to take into account physical phenomena that are hard to be captured mathematically. This platform is implemented in the HCD design architecture to reliably evaluate the design attributes and performance supercriterion during the design process. The resulting architecture is applied to redesigning kinematic, dynamic and control parameters of an industrial manipulator.     

Integrated design methodology of ball-screw driven servomechanisms with discrete controllers. Part II: Formulation and synthesis of the integrated design

In order to acquire high-speed and high-precision performances in ball-screw driven servomechanisms, an integrated design methodology has been proposed. Based on strict mathematical modeling and analysis of servomechanism performance according to design and operating parameters, a nonlinear constrained optimization problem including the relevant subsystem parameters of a ball-screw driven servomechanism is formulated. A multi-objective function and nondimensional variables are introduced in the design process. Constraints for the mechanical and control subsystems render the integrated design problem accurate. Optimum design results of the mechanical and control subsystems are obtained according to the design parameters specified by designers through the integrated design process. Motors are optimally selected from the servo motor database according to the iteration process. Both geometric errors due to Abbe offset and contour errors are minimized while required constraints such as stability and saturated conditions are satisfied. This design methodology not only optimizes the dynamic performance of the servomechanism, but also improves quality of the design process to achieve the required performance for ball-screw driven servomechanisms.     

A unified design methodology for CMOS tapered buffers

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed     

Diagnosis of Inconsistency in Contracts using Design by Contract

Design by contract allows to develop more reliable and robust applications. Software is reliable if it can perform its work as it was specified, and it is robust if it can control abnormal situations. In this paper it is proposed a methodology to diagnose errors (bugs) in software. It is based on the combination of design by contract, model based diagnosis and constraint programming. Contracts are specified in the design by contract using asserts. These asserts with an abstraction of the source code are transformed into constraints, and these constraints compose the system model. A goal function is established according to the constraints of the system model. With this function is possible to detect which asserts or source code blocks are incorrect. It is proposed a typical diagnosis problem with the design by contract and the source code. The originality of this work is based in the transformation of contracts and source code to constraints in order to obtain which asserts and source code blocks are not consistent with the specification. To obtain these results it is proposed a novel methodology that automatize this task using constraint programming.     

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.