Switching activity evaluation of CMOS digital circuits using logictiming simulation

The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitches, a main source of switching activity. Model results of a four-bit multiplier are within 4% with respect to HSPICE, while Verilog overestimations are up to 68%     

Circuit-level simulation of TDDB failure in digital CMOS circuits

An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible     

Thermal modelling of hybrid circuits: simulation method comparison

This paper presents analytical and numerical methods of hybrid circuit thermal simulation. The advantages and disadvantages of both approaches are discussed based on simulation results of a real hybrid circuit. The simulations are validated with infrared thermography measurements.     

Switched-capacitor filters using floating-inductance simulation circuits

A switched-capacitor floating-inductance-simulation circuit which is insensitive to parasitic capacitances, and a ladder-filter design technique using the simulation circuit, are presented. As an application, a lowpass filter realisation is described.     

深存储示波器调试混合信号电路

使用混合模拟和数字技术的现代嵌入式系统需要有全新一类示波器,其理由是今天的电气工程师在设计和调试现代混合信号嵌入式系统时，正面临着越来越多的测量挑战。为了向客户提供智能化程度更高的产品，他们需要使用更先进的微处理器、数字信号处理器(DSP)和现场可编程门阵列FPGA），使设计的复杂性不断提升。在机-电和生物-机械产品设计中，工程师经常需要同时采集和测量慢模拟信号和快数字信号。由于受现有仿真工具的限制，他们不能向仿真环境提供真实世界的激励，而必须经过制造原型和调试的过程。其间遇到的问题可能是间歇性的，偶尔…     

Statistical simulation of circuits using interpolation polynomials

It is shown that interpolation multivariate polynomials can be conveniently used to perform statistical simulation of circuits. This method can save computer time in Monte Carlo runs. A voltage series regulator and a TV sweep generator have been studied.     

Computer simulation of SC circuits using NAP

The adaptation of the NAP program to the frequency analysis of SC circuits is presented in the letter. According to this approach the equivalent circuit contains resistances and inductances or capacitances as the representations of the switched or unswitched capacitors in the frequency domain.     

Formal verification of component-based designs

Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex, and designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must fulfill strict requirements on reliability and correctness. This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already formally verified by their designers. The components are considered correct given that the environment satisfies certain properties imposed by the component. The methodology verifies the correctness of the glue logic inserted between the components and the interaction of the components through the glue logic. Each such glue logic is verified one at a time using model checking techniques. Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply such a verification methodology on real-life examples.     

Three-dimensional CMOL: three-dimensional integration of CMOS/nanomaterial hybrid digital circuits

The CMOS molecular (CMOL) circuit is a promising hybrid structure incorporating the nanowire crossbar into the CMOS integrated circuit (IC) implementation. In this letter, a novel three-dimensional (3D) architecture of the CMOL circuit is introduced. This structure eliminates the special pin requirement of the original CMOL designs, providing a feasible and efficient solution to build the practical CMOL circuits. In this 3D structure, the density of the nanowire crossbar is doubled. Such a high-density implementation enables the 3D CMOL technology to leap ahead of the IC roadmap by more than three generations.     

Brune-section simulation circuits using two operational amplifiers

New Brune-section simulation circuits using two operational amplifiers are proposed. A first-order allpass filter is constructed as an application using one of these simulation circuits. The measured response coincided closely with the calculated one in the frequency range less than about 10kHz.     

Timing verification of dynamic circuits

A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits     

WTLS握手协议的形式化验证

目前还未见到公开发表的对WTLS握手协议进行形式化分析的研究成果。本文首次使用密码协议分析工具集AVISPA,从机密性和鉴别两个方面,对WTLS握手协议进行了建模和验证。所得到的验证结果表明WTLS握手协议是安全的。     

Charge-coupled digital circuits

This paper describes the operation and the applications of charge- coupled shift registers for digital signals. Simple signal-regeneration stages for digital charge-coupled shift registers are analyzed and their operation is demonstrated by charge-coupled circuits made by a p-MOS process. A charge-transfer efficiency of about 99.6 percent per electrode at a clock frequency of 1 MHz was obtained in the operation of three-phase 8-bit shift registers made by the p-MOS process. Silicon-gate construction is proposed for achieving high- performance high-density structures and also two-phase charge-coupled devices.     

STATE VERIFICATION FOR SYNCHRONOUS CIRCUITS

This paper presents the techniques of implicit traversing and state verification for sequential finite state machines(FSMs) based of on the state collapsing of state transition graph(STG). The problems of state designing are described. In order to achieve high state enumeration coverage, heuristic knowledge is proposed.     

Compound noise separation in digital circuits using blind source separation

Analysis of individual noise sources in pre-nanometer circuits cannot take into account the evolving reality of multiple noise sources interacting with each other. Noise measurement made at an evaluation node will reflect the cumulative effect of all the active noise sources, while individual and relative severity of various noise sources will determine what types of remedial steps can be taken, pressing the need for development of algorithms that can analyze the contributions of different noise sources when a noise measurement is available. This paper addresses the cocktail-party problem inside integrated circuits with multiple noise sources. It presents a method to extract the time characteristics of individual noise source from the measured compound voltage in order to study the contribution and properties of each source. This extraction is facilitated by application of blind source separation technique, which is based on the assumption of statistical independence of various noise sources over time. The estimated noise sources can aid in performing timing and spectral analysis, and yield better circuit design techniques.     

Analog and digital circuits using organic thin-film transistors onpolyester substrates

We have fabricated and characterized analog and digital circuits using organic thin-film transistors on polyester film substrates. These are the first reported dynamic results for organic circuits fabricated on polyester substrates. The high-performance pentacene transistors yield circuits with the highest reported clock frequencies for organic circuits     

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.     

Novel digital filter implementations using hybrid RNS-binary arithmetic

The implementation of a FIR filter using a new hybrid RNS-binary arithmetic is presented for the first time. In the new arithmetic, the data samples are represented using RNS, and hence the carry free advantage of RNS computations is retained. However, the computation performed for each modulo is implemented using conventional binary arithmetic elements which overcome the drawback of ROM-based RNS arithmetic elements that become inefficient for large moduli. The conventional binary arithmetic elements are also faster and require less area than existing memoryless RNS arithmetic elements. It is shown that the filter structures based on the new arithmetic have better performance than those based on either the conventional binary or conventional RNS arithmetic for large moduli.     

Ring-like testing of digital circuits

Here we propose a new approach to the testing of digital devices, which can potentially save diagnostic hardware. An example is given for testing combinational devices. Estimates are given for reliability and hardware complexity, and an algorithm for designing operability tests is described.