共查询到20条相似文献,搜索用时 101 毫秒
1.
深亚微米MOSFET衬底电流的模拟与分析 总被引:1,自引:0,他引:1
利用器件模拟手段对深亚微米MOSFET的衬底电流进行了研究和分析,给出了有效的道长度,栅氧厚度,源漏结深,衬底掺杂浓度以及电源电压对深亚微米MOSFET衬底电流的影响,发现电源电压对深亚微米MOSFET的衬底电流有着强烈的影响,热载流子效应随电源电压的降低而迅速减小,当电源电压降低到一定程度时,热载流子效应不再成为影响深亚微米MOS电路可靠性的主要问题。 相似文献
2.
综述了近年来MOSFET的热载流子效应和可靠性的问题。总结了几种热载流子,并在此基础上详细讨论了热载流子注入(HCI)引起的退化机制。对器件寿命预测模型进行了总结和讨论。为MOSFET热载流子效应可靠性研究奠定了基础。 相似文献
3.
MOS沟道和衬底电流的二维分布理论建模 总被引:1,自引:1,他引:0
小尺寸MOS器件参量具有很强的分布效应,需要二维模型描述,本文从y截面流函数方程求解获得了MOS器件中的沟道电流和衬底电流二维分布解析模型,模型是横向场Er(y)和纵向场Ex(y)的函数,二维分布模型截有较充分的物理过程,可以基本反映电流密度的实际分布,模型可应用于与电流路径相关的MOS器件特性的研究,特别重要的应用领域是MOS热载流子可靠性电子学中的栅电流分布建模,选和深亚微米MOS器件的横向场 相似文献
4.
5.
对溶亚微米器件,由于工作电压下降,要求重新确定LDD和常规MOSFET在VLSI中的作用。本文从基本器件数理方程发出,对深亚微米常规及LDD MOSFET的器件特性、热载流子效应及短沟道效应进行了二维稳态数值模拟,指出了常规和LDD MOSFET各自的局限性,明确了在深亚微米VLSI中,LDD仍然起主要作用。 相似文献
6.
本文通过对影响MOSFET器件热载流子可靠性的主要因素的讨论,提出了CMOS电路中热载流子可靠性设计的一般性策略,并从电路、结构和工艺等方面提出了几种典型的应用方法。 相似文献
7.
8.
9.
深亚微米MOSFET模型研究进展 总被引:1,自引:0,他引:1
文中对在深亚微米MOSFET的器件模型研究基础上,提出了研究MOSFET模型值得注意的问题,并对如何建立深亚微米MOSFET模型作出了有益的探讨。 相似文献
10.
深亚微米薄层SOI/MOSFET’s热载流子效应分析 总被引:2,自引:2,他引:0
本文从二维模拟热载流子注入电流入手,讨论了不同硅层厚度、栅氧厚度和掺杂浓度对薄层深亚微米SOI/MOSFET’s热载流子效应的影响.模拟结果表明,对于不同的硅层厚度,沟道前表面漏结处的载流子浓度对热载流子效应起着不同的作用,有时甚至是决定性的作用.沟道前表面漏结处的载流子浓度和沟道最大电场一样,是影响薄层SOI/MOSFET’s热载流子效应的重要因素,这也就解释了以往文献中,随着硅层减薄,沟道电场增大,热载流子效应反而减小的矛盾.模拟也显示了在一定的硅层厚度变化范围内(60~100nm),器件热载流子效应 相似文献
11.
为优化槽栅器件结构 ,提高槽栅 MOSFET的性能和可靠性 ,文中用器件仿真软件对凹槽拐角对深亚微米槽栅 PMOSFET的特性影响进行了研究。研究结果表明凹槽拐角强烈影响器件的特性 :随着凹槽拐角的增大 ,阈值电压上升 ,电流驱动能力提高 ,而热载流子效应大大减弱 ,抗热载流子性能增强 ,热载流子可靠性获得提高 ;但凹槽拐角过大时 (例如 90°) ,器件特性变化有所不同 相似文献
12.
A review of critical reliability issues in submicron MOSFETs with oxynitride gate dielectrics is presented. We have focussed our attention on: substrate and gate currents in short channel MOSFETs, hot carrier induced MOSFET degradation under DC and AC stress, gate-induced drain leakage current and its enhancement due to stress, neutral trap generation due to electrical stress and degradation of analog MOSFET parameters. We have also discussed the problems of radiation induced neutral trap generation and boron penetration through the gate dielectric, which arise due to the advanced processing techniques utilized in submicron MOSFET processing. It is concluded that the use of oxynitride gate dielectrics can effectively solve several reliability issues encountered in scaling down MOSFETs to submicron dimensions. 相似文献
13.
Wang H.H.-C. Diaz C.H. Boon-Khim Liew Sun J.Y.-C. Tahui Wang 《Electron Device Letters, IEEE》2000,21(12):598-600
This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED. 相似文献
14.
15.
研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI(hot carrier injection)退化模型. 提出了一种基于L-M (Levenberg-Marquardt)算法的多目标响应全域优化提取策略,并对可靠性模型参数进行优化提取. 分析了优化过程中由于参数灵敏度过低产生的问题并提出采用递归算法求解不同时刻栅电流注入电荷量的加速计算方法. 最后,给出了最优化参数提取的结果,并且将测量值与理论值进行了比较,得到很好的一致性. 相似文献
16.
采用双曲正切函数的经验描述方法和器件物理分析方法,建立了适用于亚微米、深亚微米的LDD MOSFET输出I-V特性解析模型,模型中重点考虑了衬底电流的作用.模拟结果与实验有很好的一致性.该解析模型计算简便,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述,因此适用于器件的优化设计及可靠性分析. 相似文献
17.
18.
《Circuits and Devices Magazine, IEEE》1995,11(1):28-33
Explores the mechanisms of hot carrier degradation in n-MOSFETs. In addressing the problem of hot carrier degradation, we examine the carrier injection process, whereby electrons and holes are injected into the oxide from the channel. Next, we'll look at the processes responsible for creating damage. Third, the impact of the damage on the MOSFET's terminal characteristics is deternined. Then the damage process is modeled. Finally, we'll address ways to reduce hot carrier degradation 相似文献
19.
Balestra F. Matsumoto T. Tsuno M. Nakabayashi H. Koyanagi M. 《Electron Device Letters, IEEE》1995,16(10):433-435
The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage Vgmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of Vgmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range 相似文献
20.
R. Dreesen W. De Ceuninck L. De Schepper G. Groeseneken 《Microelectronics Reliability》1997,37(10-11)
A new measurement methodology has been developed in order to perform high-resolution measurements of the hot carrier degradation on MOSFET's. With this methodology, degradations as low as 0.01% can be measured accurately. The high resolution measurements are necessary for measuring hot carrier degradation in matched transistor pairs. This is demonstrated by comparing the degradation at different stress conditions. A linear extrapolation is not applicable when extrapolating the degradation curves from 1 % to 100 ppm. 相似文献