A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-$mu{hbox{m}}$ SiGe BiCMOS Technology

This paper demonstrates an 8-element phased array receiver in a standard 0.18-mum SiGe BiCMOS (1P6M, SiGe HBT f_t ap 150 GHz) technology for X- and Ku-band applications. The array receiver adopts the All-RF architecture, where the phase shifting and power combining are done at the RF level. With the integrations of all the digital control circuitry and ESD protection for all I/O pads, the receiver consumes a current of 100 ~ 200 m A from a 3.3 V supply voltage. The receiver shows 1.5 ~ 24.5 dB of power gain per channel from a 50 Omega load at 12 GHz with bias current control, and an associated NF of 4.2 dB (@ max. gain) to 13.2 dB (@ min. gain). The RMS gain error is < 0.9 dB and the RMS phase error is < 6deg at 6-18 GHz for all 4-bit phase states. The measured group delay is 162.5 plusmn 12.5 ps for all phase states at 6-18 GHz. The RMS phase mismatch and RMS gain mismatch among the eight channels are < 2.7deg and 0.4 dB, respectively, for all 16 phase states, over 6-18 GHz. The 8-element array can operate instantaneously at any center frequency and with a wide bandwidth (3 to 6 GHz, depending on the center frequency) given primarily by the 3 dB gain variation in the 6-18 GHz range. To our knowledge, this is the first demonstration of an All-RF phased array on a silicon chip with very low RMS phase and gain errors at 6-18 GHz. The chip size is 2.2 times 2.45 mm² including all pads.     

A Ka-band low power consumption MMIC core chip for T/R modules

This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core chip results in a gain of 9.0 dB and an output P_1dB of –3 dBm. In the transmitting mode, the gain and output P_1dB are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°. The power consumption is 150 mW in both work modes. The measured results show that the operating bandwidth, power consumption, gain, rms attenuation error and phase error have been significantly improved compared with the previous reports.     

A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process

This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 ^deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

A 24 GHz 6-Bit CMOS Phased-Array Receiver

This letter presents a 24 GHz 6 b phased-array receiver implemented in 0.13 mum CMOS. This design is based on a novel active vector generator that results in wideband quasi-quadrature vectors, which are used to synthesize the desired phase response. The active phase shifter has measured rms gain and phase errors of <0.5 dB and < 2.8deg at 23-24.4 GHz, resulting in a 6 b resolution. The phased-array receiver has a gain of 14 dB, a NF of 6 dB, a 3-dB gain bandwidth of 4.7 GHz and wideband input and output match. The chip consumes 30 mA from a 1.5 V supply with dimensions of 0.66 times 1.25 mm² including pads (0.5 times 1 mm² without pads).     

A 77-GHz MMIC power amplifier for automotive radar applications

A MMIC 77-GHz two-stage power amplifier (PA) is reported in this letter. This MMIC chip demonstrated a measured small signal gain of over 10 dB from 75 GHz to 80 GHz with 18.5-dBm output power at 1 dB compression. The maximum small signal gain is above 12 dB from 77 to 78 GHz. The saturated output power is better than 21.5 dBm and the maximum power added efficiency is 10% between 75 GHz and 78 GHz. This chip is fabricated using 0.1-/spl mu/m AlGaAs/InGaAs/GaAs PHEMT MMIC process on 4-mil GaAs substrate. The output power performance is the highest among the reported 4-mil MMIC GaAs HEMT PAs at this frequency and therefore it is suitable for the 77-GHz automotive radar systems and related transmitter applications in W-band.     

Implementation of a Microstrip Square Planar $N$-Way Metamaterial Power Divider

This paper describes a compact square-shaped 20-way metamaterial power divider implemented in microstrip technology and lumped capacitors and inductors. The divider comprises 12 square tiles exhibiting left-handed behavior and 13 square tiles exhibiting right-handed behavior arranged in a checkerboard tessellation (or mosaic). The divider relies upon the infinite wavelength phenomena in two dimensions and this requires the left-handed tiles have an insertion phase between any two of its sides equal to, but with opposite sign, of that of the right-handed tiles. To achieve tessellation, both tile types must be the same size. The design method is based upon an analytic formulation, and was applied to the realization of a 20-way power divider operating at 1 GHz that uses surface-mount lumped components. The resulting divider was 50 mm by 50 mm. Over a 10% bandwidth, the measured insertion loss was less than 1.3 dB, the measured couplings track within plusmn1 dB and plusmn6deg , and the measured input port return loss and isolation was greater than 20 dB. This level of isolation was achieved without isolation resistors. Equal in-phase power division to output ports on the square-shaped periphery allows compact integration with other planar circuit modules in a combined amplifier. The design method can be extended to N-way power division where N is an odd integer multiple of 4.     

0.18 μm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7± 17.4 ps group-delay

A3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S₁₁) of -9.7 to -19.9 dB, output return loss (S22) of-8.4 to -22.5 dB, flat forward gain (S21) 11.4 plusmn0.4 dB, reverse isolation (S12) of -40 to -48 dB, and noise figure of 4.12-5.16 dB over the 3.1-10.6 GHz band of interest. A good 1 dB compression point (Pi dB) of -7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 x 657 mum excluding the test pads.     

A 75 GHz regenerative dynamic frequency divider with active transformer using InGaAs/InP HBT technology

This letter presents a high speed 2:1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7 μm InP DHBT technology with f_T of 165 GHz and f_max of 230 GHz. The circuit includes a two-stage active transformer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer (widely known as the Gilbert cell) and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469×414 μm² and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximum output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.     

A 24−30 GHz 8-element dual-polarized 5G FR2 phased-array transceiver IC with 20.8-dBm TX OP1dB and 4.1-dB RX NFin 65-nm CMOS

This article presents an 8-element dual-polarized phased-array transceiver (TRX) front-end IC for millimeter-wave (mm-Wave) 5G new radio (NR). Power enhancement technologies for power amplifiers (PA) in mm-Wave 5G phased-array TRX are discussed. A four-stage wideband high-power class-AB PA with distributed-active-transformer (DAT) power combining and multi-stage second-harmonic traps is proposed, ensuring the mitigated amplitude-to-phase (AM-PM) distortions across wide carrier frequencies without degrading transmitting (TX) power, gain and efficiency. TX and receiving (RX) switching is achieved by a matching network co-designed on-chip T/R switch. In each TRX element, 6-bit 360° phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter (VMPS) and differential attenuator (ATT). Fabricated in 65-nm bulk complementary metal oxide semiconductor (CMOS), the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB, covering the 24−29.5 GHz band. The measured peak TX OP1dB and power-added efficiency (PAE) are 20.8 dBm and 21.1%, respectively. The measured minimum RX NF is 4.1 dB. The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude (EVM) of 5% with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz, covering 3GPP 5G NR FR2 operating bands of n257, n258, and n261.     

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.     

165-GHz Transceiver in SiGe Technology

Two D-band transceivers, with and without amplifiers and static frequency divider, transmitting simultaneously in the 80-GHz and 160-GHz bands, are fabricated in SiGe HBT technology. The transceivers feature an 80-GHz quadrature Colpitts oscillator with differential outputs at 160 GHz, a double-balanced Gilbert-cell mixer, 170-GHz amplifiers and broadband 70-GHz to 180-GHz vertically stacked transformers for single-ended to differential conversion. For the transceiver with amplifiers and static frequency divider, which marks the highest level of integration above 100 GHz in silicon, the peak differential down-conversion gain is -3 dB for RF inputs at 165 GHz. The single-ended, 165-GHz transmitter output generates -3.5 dBm, while the 82.5-GHz differential output power is +2.5 dBm. This transceiver occupies 840 mum times 1365 mum, is biased from 3.3 V, and consumes 0.9 W. Two stand-alone 5-stage amplifiers, centered at 140 GHz and 170 GHz, were also fabricated showing 17 dB and 15 dB gain at 140 GHz and 170 GHz, respectively. The saturated output power of the amplifiers is +1 dBm at 130 GHz and 0 dBm at 165 GHz. All circuits were characterized over temperature up to 125degC. These results demonstrate for the first time the feasibility of SiGe BiCMOS technology for circuits in the 100-180-GHz range.     

Low-Loss 4–6-GHz Tunable Filter With 3-Bit High-$Q$ Orthogonal Bias RF-MEMS Capacitance Network

This paper presents a low-loss 4-6-GHz 3-bit tunable filter on a quartz substrate using a high-Q 3-bit orthogonal bias RF microelectromechanical systems capacitance network. Detailed design equations for the capacitively loaded coupled lambda/2 resonators and with capacitive external coupling and source-load impedance loading are discussed. Measurements show an unloaded Q of 85-170, an insertion loss of 1.5-2.8 dB, and a 1-dB bandwidth of 4.35plusmn0.35% at 4-6 GHz. The measured third-order intermodulation intercept point and 1-dB power compression point at 5.91 GHz are > 40 and 27.5 dBm, respectively. The unloaded Q can be improved to 125-210 with the use of a thicker bottom electrode. To our knowledge, this is the highest Q tunable planar filter to date at this frequency range.     

Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Radar and Millimeter-Wave Imaging

This paper presents the first single-chip direct-conversion 77-85 GHz transceiver fabricated in SiGe HBT technology, intended for Doppler radar and millimeter-wave imaging, particularly within the automotive radar band of 77-81 GHz. A 1.3 mm times 0.9 mm 86-96 GHz receiver is also presented. The transceiver, fabricated in a 130 nm SiGe HBT technology with f_T/f_MAX of 230/300 GHz, consumes 780 mW, and occupies 1.3 mm times 0.9 mm of die area. Furthermore, it achieves 40 dB conversion gain in the receiver at 82 GHz, a 3 dB bandwidth extending from 77 to 85 GHz at 25degC, and covering the entire 77-81 GHz band up to 100degC, record 3.85 dB DSB noise figure measured at 82 GHz LO and 1 GHz IF, and an IP_1dB of -35 dBm. The transmitter provides + 11.5 dBm of saturated output power at 77 GHz, and a divide64 static frequency divider is included on-die. Successful detection of a Doppler shift of 30 Hz at a range of 6 m is shown. The 86-96 GHz receiver achieves 31 dB conversion gain, a 3 dB bandwidth of 10 GHz, and 5.2 dB DSB noise figure at 96 GHz LO and 1 GHz IF, and -99 dBc/Hz phase noise at 1 MHz offset. System-level layout and integration techniques that address the challenges of low-voltage transceiver implementation are also discussed.     

Design and performance of octave S/C band MMICT/R modules for multi-function phased arrays

A complex wideband transmit/receive module that achieves performance levels superior to any MMIC module is described. Peak performance within the octave 3.0 to 6.0 GHz band includes a power output of 21 W at S-band and 19 W at C-band, a noise figure of 3.9 to 5.0 dB, 30 to 38 dB of receive gain, 25 to 26 dBm output IP₃, 40 dB of gain control in 256 steps, dual receive channels with independent amplitude and phase control, and an 8-bit phase shifter with less than 1 degree calibrated RMS phase error. Total GaAs area is 146 mm² with 170 mm of total gate periphery. The module incorporates a compact digital interface, requires only three supply voltages, and utilizes advanced packaging techniques, resulting in a size compatible with a grating lobe free grid spacing     

A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.