一种低复杂度的稀疏FIR陷波滤波器的设计方法

FIR陷波滤波器具有线性相位、精度高、稳定性好等诸多优势,然而当陷波性能要求较高时,通常需要较高的阶数,导致FIR陷波滤波器硬件实现复杂度大大提高。该文基于稀疏FIR滤波器设计算法和共同子式消除的思想,提出一种低复杂度的FIR陷波滤波器设计方法。该方法首先采用稀疏滤波器设计算法得到满足频域性能设计要求的FIR陷波原始滤波器系数,然后对其进行CSD编码,并分析CSD编码量化系数集中所有的2项子式和孤子的灵敏度,最后根据灵敏度的大小依次选择合理的2项子式或孤子直接合成滤波器系数集。仿真结果表明,新算法设计实现的FIR陷波滤波器比已有的低复杂度设计方法最多可减少51%的加法器,有效地降低了硬件实现复杂度,大大节省了硬件资源。

     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.     

新型高速CSD编码滤波器及VLSl的实现

通过对BOOTH型乘法器、高速加法器结构和CSD编码滤波器结构的深入研究,开发出一种新型高速CSD编码滤波器结构.采用此结构实现了正交幅度调制器中的一个高速反SINC滤波器,并在ALCATEL 0.35μm CMOS工艺实现.芯片规模7500门,面积1.00mm×0.42mm.     

Design of non-uniform filter bank transmultiplexer with canonical signed digit filter coefficients

Design of non-uniform filter bank transmultiplexer (NUFB TMUX) with canonical signed digit (CSD) coefficients is presented. NUFB TMUX is preferred in a multicarrier communication system when applications with different data rates are to be multiplexed. If the filter coefficients are represented in CSD format, the hardware complexity of the NUFB TMUX can be reduced. A continuous coefficient NUFB TMUX is designed and the coefficients of the filters are synthesised in CSD format using genetic algorithm (GA). Separate objective functions are formulated for the fitness evaluation of the filters. Chromosomes are encoded as ternary digit strings. New crossover and mutation techniques are introduced to preserve the canonical property of the signed power of two (SPT) representations. For the fast convergence of the GA, positiondependent probability of mutation is used. Simulation results show that the CSD coefficient NUFB TMUX designed using the proposed algorithm has better signal-to-interference ratio (SIR) than that of continuous coefficient NUFB TMUX and CSD coefficient NUFB TMUX obtained by rounding. Frequency responses of its filters are better than that of the filters in CSD coefficient NUFB TMUX obtained by rounding and comparable with that of continuous coefficient NUFB TMUX.     

A flexible adaptive FIR filter VLSI IC

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described     

可编程FIR滤波器的FPGA实现

介绍了FIR滤波器的基本的线性相位结构及FIR滤波器的抽头系数SD算法编码。给定滤波器的数字指标,用MATLB设计抽头系数,最后用Verilog HDL语言实现了一个16阶的FIR低通滤波器并在QuartusⅡ上仿真,并对仿真结果与理论值进行比较,波形仿真结果和理论值相吻和,最后将编程数据文件下载到FPGA芯片上。对于不同性能的FIR滤波器,抽头系数是变化的,因此只要对本设计的抽头系数重新在线配置,就可以实现不同的FIR滤波器。     

Low-power and area-efficient FIR filter implementation suitable for multiple taps

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-/spl mu/m CMOS technology with three levels of metal. The chip that occupies 2.3/spl times/2.5 mm/sup 2/ of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V/sub dd/=3.3 V.     

Realization of 2-D linear-phase FIR filters by using thesingular-value decomposition

The singular-value decomposition (SVD) technique is investigated for the realization of a general two-dimensional (2-D) linear-phase FIR filter with an arbitrary magnitude response. A parallel realization structure consisting of a number of one-dimensional (1-D) FIR subfilters is obtained by applying the SVD to the impulse response of a 2-D filter. It is shown that by using the symmetry property of the 2-D impulse response and by developing an appropriate unitary transformation, an SVD yielding linear-phase constituent 1-D filters can always be obtained so that the efficient structures of the 1-D linear-phase filters can be exploited for 2-D realization. It is shown that when the 2-D filter to be realized has some specified symmetry in its magnitude response, the proposed SVD realization would yield a magnitude characteristic with the same symmetry. An analysis is carried out to obtain tight upper bounds for the errors in the impulse response as well as in the frequency response of the realized filter. It is shown that the number of parallel sections can be reduced significantly without introducing large errors, even in the case of 2-D filters with nonsymmetric magnitude response     

A high-speed digitally programmable CCD transversal filter

A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible.     

A Low-Power Digit-Based Reconfigurable FIR Filter

In this brief, we present a digit-reconfigurable finite-impulse response (FIR) filter architecture with a very fine granularity. It provides a flexible yet compact and low-power solution to FIR filters with a wide range of precision and tap length. Based on the proposed architecture, an 8-digit reconfigurable FIR filter chip is implemented in a single-poly quadruple-metal 0.35-$muhbox m$CMOS technology. Measurement results show that the fabricated chip operates up to 86 MHz when the filter draws 16.5 mW of power from a 2.5-V power supply.     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process     

A Miniaturized Bandwidth Reconfigurable Bandpass Chip Filter with Semi-lump ed Topology and GaAs pHEMT Technology

A miniaturized reconfigurable bandpass chip filter with semi-lumped topology and Gallium Arsenide pseudomorphic High electron mobility transistor (GaAs pHEMT) technology is proposed. Semi-lumped topology is employed to instead the traditional lumped inductor with microstrip transmission line, which can reduced the size of the tunable filter significantly. Three-order series and shunt resonated bandpass filter is implemented with shorted stubs and metal-insulator-metal capacitors. Two transmission zeros are introduced with the series resonator and the shunted GaAs FET. By tuning the gate bias circuit of the FET, the capacitance of the series resonator is changed and the bandwidth of the filter is adjusted correspondingly. An equivalent circuit model is developed to interpret the mechanism of the proposed filter circuit. A reconfigurable on chip filter sample operated at 10GHz is fabricated to validate the design. Two fractional bandwidth of 14.3％and 23.5％are tuned with bias voltage of the FET, while insertion loss of 2.4dB and 2.2dB are observed with the filter, respectively. The area of the chip filter is 0.86 × 0.96mm2 and is equivalent to an electrical length of 0.08 × 0.09λg2 at center frequency. Measurement results agree well with the simulation ones.     

基于DFT滤波器组的低时延FPGA语音处理实现研究

提出了WOLA（Weighted Overlap-Add）并行结构的低时延DFT滤波器组的设计和FPGA实现方法.为降低系统总体时延,在综合考虑传递失真、混迭失真的基础上,将群时延引入系统目标函数,并采用非对称综合原型滤波器设计方法,提出迭代算法,实现了DFT滤波器组低时延优化设计.通过对DFT滤波器组中分析和综合功能的关键模块采用多路并行乘法、多级流水加法链设计,实现了并行的WOLA结构DFT滤波器组,降低FPGA实现的计算时延.整个设计在Xilinx公司的Zynq7020型号FPGA芯片上进行实现.PESQ测试表明,设计的DFT滤波器组能取得较好的语音质量.与串行WOLA结构的实现对比表明,在16kHz语音采样率下,并行的WOLA结构FPGA实现的总时延能降低1.192ms,其中群时延降低12%,计算时延降低29.2%.     

A single-chip video ghost canceller

A 450 K-transistor video ghost canceller chip, which implements a flexibly configurable IIR and FIR filter, is described. A very compact digital filter tap operating at a pixel rate of 14.32 MHz (4×F _sc) allows 180 programmable taps to be implemented in a die area of 56.25 mm² in a 1 μm TLM CMOS process. The device operates with 3.3- or 5-V power supplies     

Linear-phase FIR interpolation, decimation, and mth-band filters utilizing the farrow structure

This paper introduces novel linear-phase finite-impulse response (FIR) interpolation, decimation, and Mth-band filters utilizing the Farrow structure. In these new overall filters, each polyphase component (except for one term) is realized using the Farrow structure with a distinct fractional delay. The corresponding interpolation/decimation structures can therefore be implemented using only one set of linear-phase FIR subfilters and one set of multipliers that correspond to the distinct fractional delays. The main advantage of the proposed structures is that they are flexible as to the conversion factors, and this also for an arbitrary set of integer factors, including prime numbers. In particular, they can simultaneously implement several converters at a low cost. The proposed filters can be used to generate both general filters and Mth-band filters for interpolation and decimation by the integer factor M. (In this paper, a general filter for interpolation and decimation by M means a filter having a bandwidth of approximately /spl pi//M without the restriction that /spl pi//M be included in the transition band. This is in contrast to an Mth-band filter whose transition band does include /spl pi//M.) In both cases, the overall filter design problem can be posed as a convex problem, the solution of which is globally optimum. Design examples are included in the paper illustrating the properties and potentials of the proposed filters.     

FIR滤波器的FPGA高效实现和巧妙验证

为了降低FIR滤波器对FPGA资源的消耗,同时能够直接验证其滤波性能,本文介绍了基于加法器网络的FIR滤波器的实现方法,以及系数的CSD码、最优CSD码表示方法,并引出了更加高效的简化加法器网络法.以一个32阶FIR低通滤波器的实现为例说明了设计的过程,巧妙结合MATALB与QuartusⅡ对所设计的滤波器进行了验证.实践表明,该方法节约资源,调试方便.     

A surface-charge correlator

Surface-charge transfer techniques have been used to implement a cross-correlator module in which the tap weights are restricted to values of plus and minus one. This compromise permits most of the advantages of CTD's to be retained, and the disadvantage of fixed tap weights can be overcome by using a weighted binary code for the tap weight function and separate binary correlators for each binary digit. A new architecture (parallel transfer) was used which eliminates the cumulative effect of charge-transfer inefficiency, thereby permitting longer impulse responses to be implemented than is practical with the conventional series transfer approach. The experimental device, which contains 32 stages, was implemented in p-channel MOS technology, and was designed to operate at 4 MHz. Test results are presented showing that a tap weight accuracy of order 1/2 percent can be achieved on a single chip. Presuming that the modular approach employed permits selection of well-matched chips with leakage at least as low as was obtained in the experimental units, it would be possible to implement an impulse response covering 40000 samples with tap weight accuracy of perhaps 1 percent.     

一种16位音频∑△ A/D转换器

提出了一种16位立体声音频新型稳定的5阶∑△A/D转换器.该转换器由开关电容∑△调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm 5V CMOS工艺实现∑△A/D转换器.∑△A/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

Design of linear-phase IIR filters via impulse-response gramians

A new method for the design of a linear-phase infinite-impulse-response (IIR) filter is presented. It involves designing a finite-impulse-response (FIR) filter satisfying the given frequency response specifications and subsequently obtaining a significantly lower order IIR filter using model reduction based on impulse-response gramians. The general outline of the method and a brief overview of the existing linear-phase FIR filter design and model-reduction techniques are presented. The impulse-response gramian and the model-reduction algorithm used are presented. The method is illustrated by design examples and is compared with other methods for the design of linear-phase IIR filters using equalizers