Low-power CSD linear phase FIR filter structure using verticalcommon sub-expression

A high-speed/low-power canonic signed digit (CSD) linear phase finite impulse response (FIR) filter structure using vertical common sub-expression is proposed. In the conventional linear phase CSD filter, the horizontal common sub-expression method (see Hartley, 1996) has been widely utilised due to the inherent symmetrical filter coefficients. However, use has been made of the fact that the most significant bits of adjacent filter coefficients in the linear phase filter are also equal since they have mostly similar values. Through the example, it is shown that the proposed structure is more efficient in the case where bit precision of implementation is lower     

Digitally programmable switched-current FIR filter for low-voltageapplications

In this paper, we describe a switched-current (SI) finite-impulse response (FIR) filter, suitable for equalizer architectures. The basic cell of the FIR filter is a SI sample-hold (S/H) circuit, appropriate for low-voltage operation. The programmability of the FIR filter structure is achieved via MOSFET-only current dividers. The FIR filter has been designed and implemented using a 0.8 μm CMOS process and operates at a power-supply voltage of 2 V     

Increased precision digital filter coefficients using digitaldither

The DF1 (direct form 1) IIR filter structure is the most common structure employed in audio applications. The author explores the application of digital dither to increase the precision of filter coefficients allowing up to double precision performance to be achieved with single precision arithmetic. This realisation provides a versatile DF1 realisation suitable for many applications     

FIR digital filter design techniques using weighted Chebyshev approximation

This paper discusses the various approaches to designing FIR digital filters using the theory of weighted Chebyshev approximation. The different design techniques are explained and compared on the basis of their capabilities and limitations. The relationships between filter parameters are briefly discussed for the case of low-pass filters. Extensions of the theory to the problems of magnitude and complex approximation are also included, as are some recent results on the design of two-dimensional FIR filters by transformation.     

基于CSD编码遗传算法的FIR滤波器优化设计

本文主要研究了采用CSD(canonic signed digit)编码的遗传算法对FIR(Finite Impulse Response)滤波器系数进行的有限精度优化,并对传统的CSD编码方法进行了改进,使之能够更快地收敛到最优解.针对CSD编码经过交叉、变异后可能出现的问题,提出了解码替代的解决方法.在级联滤波器的设计中,采用了波纹互相抵消技术使设计的级联滤波器通带内纹波大大降低.     

A programmable pipelined digital differential matched filter forDSSS receiver

A programmable pipelined digital differential matched filter (PDMF) implemented for a direct sequence spread spectrum receiver is proposed in this paper. To reduce the power consumption, the PDMF architecture is based on the synchronization combined PN code phase acquisition algorithm. Compared with the conventional PN code phase acquisition algorithm, the theoretical analysis result indicates that the PDMF acquires both power efficient and preferable detection. Depending on different applications, programmability allows the PDMF to implement 3-tap, 5-tap, or 11-tap Barker codes with the same hardware but different precisions for each tap coefficient. For short tap Baker codes, the architecture could adopt more precision on each tap coefficient to resist the channel noise. Simulation results also show that there are fewer errors of high sample precision with the same tape     

A new method for higher-order linear phase FIR digital filter using shifted Chebyshev polynomials

In this work, a new method for the design of linear phase finite impulse response (FIR) filters using shifted Chebyshev polynomial is proposed. In this method, magnitude response of FIR filter is approximated with the help of shifted Chebyshev polynomials. The number of polynomials used for approximation depends upon the order of filter. Design problem of filter is constructed as minimization of integral mean-square error between the ideal response and actual response through differentiating it with respect to its coefficients, which leads to a system of linear equations. The simulation results included in this paper show the efficiency of proposed method. It is also evident from the results that the proposed method is suitable for higher filter taps.     

FIR数字滤波器的设计与实现

以窗函数法设计FIR数字滤波器,利用MATLAB工具软件辅助设计和仿真,对信号进行低通滤波,并使用CCS应用软件进行仿真及调试,实现了DSP下数字低通滤波器的设计.     

Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.     

A class of high-precision multiplier-free FIR filter realizationswith periodically time-varying coefficients

Proposes a class of high-precision, multiplier-free realizations for FIR filters. These realizations use upsampling and downsampling in conjunction with a periodically time-varying system to achieve time-invariant, multiplier-free FIR filter operation. Nonbinary encoding schemes are used for obtaining the filter coefficients, which are periodically time-varying (PTV), i.e., they vary in a periodic fashion. Each target filter coefficient is directly mapped into a set of PTV coefficients so that the realizations are easy to obtain. The values of the PTV coefficients are restricted to either the ternary set {±1, 0} or the quinary set {±2, ±1, 0} so that the realizations can be implemented with only add/subtract and one-bit shift (for the quinary case) operations. A few shift-and-add operations are also needed at the beginning and the end of the structure. Coefficient precisions (in bits) of these realizations are given and they are sufficiently high for most applications. Advantages of the proposed realizations accrue at the expense of a higher clock rate     

Vlsi programmable digital filter for video signal processing

High speed digital filtering is required in real time video signal processing, as well as high order filters are needed to match television studio signal quality. The hardware complexity involved by such system constraints may be faced by a two-fold approach, concerning both the architecture and the technological aspects of a specific electronics device devoted to the above task.This article deals with a processor especially developed for the purpose of fast digital video signal applications, such as filtering, equalization, interpolation and so on. The nonrecursive transposed F.I.R. (Finite Impulse Response) structure has been selected, which exhibits a linear phase behavior. A novel approach has been developed for the multipliers implementation, by optimizing an EPROM based look-up table storing the products between all video samples and the filter coefficients significant bits, resulting in a programmable system.TheProgrammable Filter Processor has been designed with a high level of parallelism and pipelining and a 1.2 µm CMOS EPROM, single metal technology has been employed for the integration process of the chip. This has been successfully production-tested for 40 Msamples/s throughput rate, thus both allowing to meet most video filtering applications and demonstrating the potentialities of nonvolatile memory technologies in embedded applications.Moreover multiple devices can be interconnected to yield multiprocessor structures for more demanding performances such as, cascaded or longer filters, input signal precision extension, computation improved accuracy, increased throughput rate, and two-dimensional signal processing.Work carried out in the framework of the agreement between the Italian P.T. Administration and the Fondazione UGO BORDONI.     

基于FPGA和Matlab的FIR数字滤波器

为了满足信号处理快速和灵活的要求,基于FPGA实现的FIR滤波器有这两方面的优势,使用Matlab中的FDATool计算出滤波器系数并分析其幅频特性,利用FPGA分别设计实现串行结构、全并行结构以及基于IP核的FIR数字滤波器。利用Matlab软件进行FIR滤波器仿真,并与基于FPGA实现滤波器的Modelsim仿真输出数据进行比较,结果表明,设计的FIR滤波器功能正确、滤波性能良好。通过对不同结构滤波器的资源占用情况和数据处理速度进行分析,得出不同应用场合可选择不同的滤波器结构的结论。     

基于FPGA的FIR滤波器的性能研究

目前FIR滤波器的一般设计方法比较繁琐,开发周期长,如果采用设计好的FIR滤波器的IP核,则开发效率大为提高。本方案基于Altera公司的Cyclone Ⅱ系列芯片EP2C8Q208C8N,首先利用MATLAB中的滤波器函数fir2得出需产生的FIR滤波器的系数,再导入FIR IP Core,成功完成了FIR数字滤波器的设计。另外分析了阶数与不均匀采样数据对FPGA资源的影响和对生成FIR滤波器的输出性能的影响,并将实际输出的幅频特性图与我们需要的幅频特性图相比较,验证生成的FIR数字滤波器的性能。     

FIR数字滤波器的FPGA实现研究

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能,在Xilinx ISE10.1开发平台中,采用Verilog HDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构,并在ModelSim仿真验证平台中仿真了实现设计.结果表明,改进串行结构的实现消耗资源少但滤波速度慢,并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少.     

FIR数字滤波器的FPGA实现研究

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能．在Xilinx ISE10．1开发平台中,采用VerilogHDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构。并在ModelSim仿真验证平台中仿真了实现设计。结果表明,改进串行结构的实现消耗资源少但滤波速度慢．并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少。     

Design of minimum-phase FIR digital filter through cepstrum

A method to design an equiripple minimum-phase FIR filter using the cepstrum is described. This method avoids the complicated polynomial root-finding algorithm of Herrman and Schuessler (1970), or the phase-unwrapping algorithm associated with the complex cepstrum of Mian and Nainar (1982). The differential cepstrum method proposed by Pei and Lu (1986) has aliasing problems and requires the computation of three FFTs. The proposed method requires only two FFT computations and avoids the processing of phase.     

Comments on "FIR digital filter design techniques using weighted Chebyshev approximation"

The history of the FIR filter approximation problem, as recently presented by Rabiner, McClellan, and Parks, is deficient in some areas and misleading in others. Some corrections are suggested. In addition to a brief discussion of different approaches to the design of FIR digital filters, areas into which present methods can be readily extended are outlined. The relationship between the parks and McClellan method and the upper and lower function method is presented.     

A fully programmable sampled-data analog CMOS filter with transfer-function coefficients determined by timing

A CMOS analog signal processor which is as programmable as a digital one is discussed. This processor does not use known switched-capacitor techniques, nor does it contain any selectable capacitor (or resistor) arrays. Instead, it operates on a pulsewidth control principle in which the value of each branch gain is determined by the duty cycle of a single digitally controlled analog transmission gate. A 4-/spl mu/m single-poly CMOS test IC containing all the critical analog functions was designed to demonstrate this principle at sampling frequencies up to 100 kHz. All of the processors described allow individual programming of each transfer function coefficient; one also features programmable topology, and another is capable of simultaneous multiple-signal multiple-transfer-function processing. A typical integrated fully programmable biquad shows 80-dB dynamic range.     

An 85-MHz fourth-order programmable IIR digital filter chip

The authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each, and the output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10×10 multiply-add modules are used in this chip. The chip contains 80000 devices in an active area of 14 mm². It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5×10⁹ multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed