SCR 器件在深亚微米CMOS静电保护电路中的应用

:CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制.因此,对ESD保护的要求也更加严格,需要采取更加有效而且可靠的ESD保护措施.针对近年来SCR器件更加广泛地被采用到CMOS静电保护电路中的情况,总结了SCR保护电路发展过程中各种电路的工作机理.旨在为集成电路设计人员提供ESD保护方面的设计思路以及努力方向.     

深亚微米CMOS IC抗噪声ESD保护电路的设计

CMOS工艺技术缩小到深亚微米阶段，电路的静电(ESD)保护能力受到了更大的限制。因此，需要采取更加有效并且可靠的静电放电保护设计。文章提出了一种新型的ESD保护电路，以LVTSCR结构为基础，结合栅耦合技术以及抗噪声干扰技术。这种新型电路即使被意外触发也不会引起闩锁效应，提高了ESD保护电路的可靠性，实现了全芯片保护。     

亚微米CMOS集成电路的ESD保护新结构

本文主要介绍几种新型的ESD保护结构,包括互补SCR结构,双寄生SCR结构,低触发电压,高触发电流的横向SCR结构等,利用这些结构可以对CMOS集电路的输入／输出进行有效地ESD保护。     

基于CMOS工艺的IC卡芯片ESD保护电路

介绍了ESD保护结构的基本原理,并提出一个基于CMOS工艺用于IC卡芯片的保护电路.讨论了一些重要的设计参数对ESD保护电路性能的影响并进行了物理上的解释.     

TFSOI/CMOS ESD研究

文章讨论了TFSOI／CMOS中ESD电路与常见体硅ESD电路的主要区别,详细分析了ESD电路中各个组成部分对整体性能的影响,成功地研制了抗2000V静电的ESD保护电路,指出了进一步提高TFSOI／CMOS ESD抗静电能力的途径。     

CMOS集成电路中ESD保护技术研究

分析ESD失效的原因和失效模式,针对亚微米CMOS工艺对器件ESD保护能力的降低,从工艺、器件、电路三个层次对提高ESD保护能力的设计思路进行论述。工艺层次上通过增加ESD注入层和硅化物阻挡层实现ESD能力的提高;器件方面可针对电路的特点,选择合适的器件(如MOS,SCR,二极管及电阻)达到电路需要的ESD保护能力;电路方面采用栅耦和实现功能较强的ESD保护。     

基于CMOS工艺的芯片ESD设计

随着射频电路工作频率不断升高,ESD已经成为影响电路可靠性和射频电路性能的重要因素。针对高速射频电路,设计了高速I/O口ESD防护电路和电源到地的箝位电路,并采用斜边叉指型二极管进行版图和性能优化。采用Jazz 0.18μm SiGe BiCMOS工艺对ESD防护电路进行设计和流片。经过测试得出,ESD保护电压最高可达到3000V。更改二极管叉指数取得更高的ESD防护级别,改进后保护电压最高可达到4500V。文中阐述了ESD防护架构的基本原则,并给出了一种采用CMOS工艺设计应用于IC卡晶片上的防护工作电路。探讨了几个关键设计参数及其对ESD保护电路特性的影响,并做出了物理上的说明。     

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.     

深亚微米CMOS IC全芯片ESD保护技术

CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制。因此,需要采取更加有效而且可靠的ESD保护措施。基于改进的SCR器件和STFOD结构,本文提出了一种新颖的全芯片ESD保护架构,这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。     

基于CMOS多功能数字芯片的ESD保护电路设计

基于CSMC 2P2M 0.6 μm CMOS工艺设计了一种ESD保护电路。整体电路采用Hspice和CSMC 2P2M 的0.6 μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6 μm CMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1 mm×1 mm,参与MPW(多项目晶圆)计划流片,流片测试结果表明,芯片满足设计目标。     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.     

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the base or substrate of the SCR device, it can be quickly triggered into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR devices can be stacked in ESD protection circuits to avoid the transient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices can be reduced from 27.4 to 7.8 ns by the substrate-triggering technique. The substrate-triggered SCR device with a small active area of only 20 /spl mu/m /spl times/ 20 /spl mu/m can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-/spl mu/m CMOS process.     

Complementary-SCR ESD protection circuit with interdigitatedfinger-type layout for input pads of submicron CMOS IC's

A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 μm CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.