High Temperature Characteristics of Coplanar Waveguide on R-Plane Sapphire and Alumina

This paper presents the characteristics of coplanar waveguide transmission lines on R-plane sapphire and alumina over the temperature range of 25 $^{circ}$ C–400 $^{circ}$ C and the frequency range of 45 MHz–50 GHz. A thru-reflect-line calibration technique and open circuited terminated stubs are used to extract the attenuation and effective permittivity. It is shown that the effective permittivity of the transmission lines and, therefore, the relative dielectric constant of the two substrates increase linearly with temperature. The attenuation of the coplanar waveguide varies linearly with temperature through 200 $^{circ}$C, and increases at a greater rate above 200 $^{circ}$ C.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-$mu$ m-thick parylene-N layer and 0.56 dB/mm for a 50- $Omega$ CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with underpasses that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-$mu$ m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of ${+}$ 4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.      

A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC Converter in 0.13-$mu$ m CMOS Technology

In this work, a new termination technique for the averaging network of the flash analog-to-digital converter (ADC) input preamplifiers is devised. The proposed technique eliminates the over-range voltage headroom consumed by the dummy preamplifiers and therefore, the input capacitance and power dissipation of the ADC is reduced. This technique is applied to the design of a 6-bit 1.6-GS/s flash ADC in 0.13-$mu$ m CMOS technology. The measured peak INL and DNL are 0.42 LSB and 0.49 LSB, respectively. The ADC achieves an effective resolution bandwidth (ERBW) of 800 MHz and an SNDR of 30 dB at 1.45-GHz input signal frequency while consuming 180 mW.      

A 27 GHz, 14 dBm CMOS Power Amplifier Using 0.18 $mu {rm m}$ Common-Source MOSFETs

A Ka-band three-stage CMOS power amplifier was designed and fabricated using 0.18 $mu {rm m}$ gate-length common-source transistors. For low loss and accurate matching networks for the amplifier, a substrate-shielded microstrip-line was used with good modeling accuracy up to 40 GHz. The measured insertion loss was 0.5 dB/mm at 25 GHz. The three-stage amplifier achieved a 14.5 dB small-signal gain, 14 dBm output power, and 13.2% power-added-efficiency at 27 GHz in a compact chip area of 0.84 ${rm mm}^{2}$. The measured gain was the highest for Ka-band power amplifiers using common-source transistors. These results were achieved at a voltage compatible with deep sub-micrometer CMOS technology.      

Reconfigurable CMOS Tuners for Software-Defined Radio

A reconfigurable tuner is demonstrated by using a low-loss shielded coplanar waveguide transmission line periodically loaded with CMOS transistor switches in series with capacitors. The switch–capacitor combination is used to change the local impedance of the transmission line in a binary fashion. It achieves a higher capacitance ratio (by 60%), less transmission loss (by 40%), higher quality factor (by 100%), and subsequently wider bandwidth and better Smith impedance chart coverage compared to optimized CMOS varactors realized in the same technology. The 5–16-GHz tuner demonstrated here is implemented in a standard 0.13-$mu{hbox{m}}$ CMOS technology and can be configured to ${hbox{2}}^{20}$ different impedances through an integrated 20-bit shift register.      

Analysis and Design of a Chip Filter With Low Insertion Loss and Two Adjustable Transmission Zeros Using 0.18- $mu{hbox{m}}$ CMOS Technology

This paper presents the structure of a high-selectivity bandpass filter that is fabricated on low-resistivity silicon substrate with a commercial CMOS technology. The filter is constructed using crossed coplanar waveguide (CPW) lines and metal–insulator–metal capacitors to ensure that it has the desired passband characteristics. An adjustable capacitor between the input and output ports is employed to form a capacitive cross-coupled path, yielding two transmission zeros in the lower and upper stopbands, respectively. Additionally, the coupling mechanism can be modified by turning on or off the gate of an nMOS transistor to adjust the positions of the transmission zeros by applying an externally controlled voltage. To obtain a low passband loss and to minimize the chip size, high-impedance CPW transmission lines are adopted. Our analysis indicates that the CPW line possesses more advantages than the preferred stacked-ground CPW line for constructing the proposed filter. A very compact $X$ -band experimental prototype with a size of ${hbox{0.88}}times {hbox{0.54}} {hbox{mm}}^{2}$ was designed and fabricated. The measurements reveal an insertion loss of less than 3.2 dB in the passband, which is from 10.6 to 12.7 GHz, and rejection levels greater than 35 dB at the designed frequencies of transmission zeros. Moreover, the lower and upper transmission zeros can be shifted from 5 to 6.5 GHz and from 18 to 21.4 GHz, respectively, by changing the controlled voltage.      

An Accurate $C$– $V$ Measurement Method for Highly Leaky Devices—Part I

Accurate $C$–$V$ measurement becomes extremely difficult in advanced CMOS technology due to a high level of leakage across the gate dielectric. Recently, a new time-domain reflectometry (TDR)-based $C$–$V$ measurement method was introduced. This new method offers ease of use and high accuracy while being able to handle a very high level of leakage current. It also allows series resistance and overlap capacitance to be extracted simultaneously and accurately without the need for additional measurement. In this paper, the theoretical basis of the TDR $C$–$V$ method is described in detail, along with experimental results.      

Subthreshold Parallel FM-to-Digital $Delta$– $Sigma$ Converter With Output-Bit-Stream Addition by Interleaving

Single and parallel subthreshold frequency-modulation-to-digital $Delta$–$Sigma$ modulators (FDSMs) have been implemented in a standard 90-nm CMOS technology. Theoretical and measured results are presented for both topologies. The 512-stage parallel FDSM adopts a tunable delay line and achieves bit-stream addition by interleaving at the output stage. This architecture, with respect to the conventional parallel FDSM, reduces power, area, and complexity at the cost of using clocks with higher speed in its output stage. In addition, compared to the single FDSM, the parallel converter shows an improvement in signal-to-quantization-noise ratio of more than 25 dB at supply voltages as low as 300 mV.      

0.13 $mu$ m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

This paper presents a complete 0.13$,muhbox{m}$ SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz ${rm f}_{rm T}/{rm f}_{rm MAX}$) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 $hbox{fF}/muhbox{m}^{2}$ high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.      

A GaAs Junction Varactor With a Continuously Tunable Range of 9 : 1 and an of 57 dBm

In this letter, a junction varactor is presented with a large capacitance tuning range, while providing very high linearity. Such varactors are extremely useful in adaptive RF applications, which directly benefit from passive components with high tuning range and high linearity. Using a preproduction GaAs process technology and third-order intermodulation $(IM_{3})$ cancellation techniques, a very linear device is created with a capacitance tuning range as large as 9 : 1 over a control voltage range from 0 to 15 V. Its third-order output intercept point is 57 dBm; the average quality factor is $sim$50, and the breakdown voltage is 28 V. These measured results represent the current state-of-the-art in tuning range, linearity, and quality factor among all existing continuously tunable elements.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields

A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slot-type floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

A 1.8 V 900 $mu$ W 4.5 GHz VCO and Prescaler in 0.18 $mu$m CMOS Using Charge-Recycling Technique

This letter presents a charge-recycling VCO and divider in 0.18 $mu$m CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 $mu$W of power consumption and ${-}184$ dBc/Hz of FoM at 1.8 V.      

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $kappa$ Gate Dielectrics

The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-$kappa$ gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to a conventional MOSFET due to its totally different working principle. It turns out that the fringing field effect, while deteriorating conventional MOSFET characteristics, leads to a much higher on-current comparable with actual conventional MOSFETs, a subthreshold slope of the tunnel FET lower than the theoretical limit for conventional MOSFETs, and a massive improved inverter delay, underlining its prospect for future applications. This leads to the conclusion that high-$kappa$ materials with permittivities $≫$ 30 can advantageously be used in CMOS technology, giving rise to further technological development.      

Ring Oscillator Technique for MOSFET $CV$ Characterization

A technique for extracting small signal MOSFET gate capacitance as a function of bias voltage from measurements of circuit delay and power is described. This approach makes use of a ring oscillator with stages in which an independent bias voltage is applied to the gates of MOSFETs driven by an inverter. The square wave signal circulating around the ring oscillator, at a reduced power supply voltage, serves as a small signal excitation for the $CV$ characterization. Gate charging times of order 40 ps enable capacitance measurement in the presence of the high parallel conductance of thin gate dielectrics. MOSFET parameters such as inversion and depletion capacitances and electrical channel length can be self-consistently compared with circuit power/performance, all derived as averages over hundreds of MOSFETs from the same test structure. This minimizes dependencies on layout, spatial and statistical variations, as well as other ambiguities that can exist when a variety of test structures is used to evaluate different MOSFET and circuit performance parameters. At $≪$1 MHz, the frequency divided output is compatible with standard in-line test. Data from experimental partially depleted silicon-on-insulator hardware at the 65-nm CMOS technology node are presented.      

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4–22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79–96 GHz) despite their standard multistage designs. These amplifiers are based on an identical transistor array interconnected with application specific coplanar waveguide (CPW) transmission lines and on-chip capacitors and resistors. CPW lines are implemented using a one-metal-layer post-processing technology over a thick Parylene-N (15 $mu{hbox{m}}$ ) dielectric layer that enables very low loss lines ( $sim$0.6 dB/mm at 20 GHz) and high-performance CMOS amplifiers. The proposed integration approach has the potential for implementing cost-efficient and high-performance RF and microwave circuits with a short turnaround time.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A 4–17 GHz Darlington Cascode Broadband Medium Power Amplifier in 0.18-$mu$ m CMOS Technology

This letter presents a broadband medium power amplifier in 0.18- $mu$m CMOS technology. The Darlington cascode topology is used to achieve wide bandwidth, flat gain and power frequency response. For wideband matching consideration, an interstage inductor and series peaking RL circuit are adopted. An output high pass matching circuit is used to maintain gain and power flatness at high frequency. The measured results show that the proposed PA demonstrates a gain of 10 dB from 4 to 17 GHz with less than 2-dB ripple, and a saturation output power of 16 to 18 dBm with PAE of better than 10% and power consumption of 306 mW. The chip size is only 0.67 mm$^{2}$ .