耗散介观RLC串并联电路的量子涨落

借鉴阻尼谐振子正则量子化的方法,实现了对耗散介观RLC串并联电路的量子化,并在此基础上,研究了真空态下电路中电荷和自感磁通链、电压和电流的量子涨落。结果表明,电路中电荷和自感磁通链、电压和电流在真空态下都具有各自的量子涨落,且量子涨落及量子涨落积的大小皆与电路中的器件参数有关,并随时间按指数规律衰减。     

对初始电荷不同的两电容串、并联后的暂态分析

本文对初始电荷不同的两电容串、并联后其电压在线性动态电路中的暂态问题进行了分析,并针对因未明确"换路定理"的适用条件而犯错的几种情况进行了讨论,给出了换路定理的适用条件,通过举例说明此类问题的具体解决方法。     

换路后两个连接电容电场能量变化分析

在＂电路理论＂课程暂态分析中,换路后两个电容直接并联,或两个电感直接串联,电容电压和电感电流不再服从换路定律,当电荷与磁链重新分配后满足电荷、磁链守恒,但静电场能量与磁场能量均有损失,看似系统能量不守恒。本文将从串联暂态电量、串联稳态电压整体、并联稳态电压分体和功率密度等角度分析了能量变化,最终从线损耗和电磁辐射两方面...     

开关网络初始条件的确定

本文在有限电荷和磁通的假设下,提出了确定线性和非线性开关网络初始条件的方法.在时域分析中,获取开关动作引起一系列初始条件是求整个电路响应的关键。     

介观分布参数电路的量子效应

通过提出了一个非耗散的分布参数电路的量子化方案,采用正则与么正变换方法来研究真空态电荷与磁通的量子涨落,结果表明分布参数电路的量子涨落既与电路参数及其位置有关,也与信号模态有关.     

用0-等效电路分析常规网络的突变与守恒

在电路分析中,电荷守恒和磁链守恒常被用于换路瞬间电容电压和电感电流的突变问题,因为只涉及0-与0 两个时刻,可称之为状态分析,实际上反映的是系统电荷或磁链的连续性问题.本文导出了常规网络电荷守恒和磁链守恒的条件,并就守恒与不守恒两种情况利用0-等效电路的模型进行过程分析,最后证明了不守恒的差额恰好满足更大系统的守恒.     

对动态奇异电路的初始值问题的研究

在动态电路的时域分析中,若要解出描述电路的微分方程或状态方程,首先必须知道电路的初始状态。可是对含有纯电容回路和纯电感割集的奇异电路,在“换路”瞬间其初始值有可能发生跃变现象,不能用换路定则来求解。文章对此类电路中的初始值进行了详细的分析。通过深入探讨,给出了奇异电路中电容电压和电感电流初始值的确定方法,并给出了几个应用实例。     

基于开关电容技术的磁通门选频放大电路研究

传统磁通门信号处理电路中的选频放大电路由运放和电阻电容网络构成的多环反馈型带通滤波器组成,具有电路结构简单、可靠性高、成本低等特点.但电路中电阻、电容的值较大,不易集成.基于将磁通门传感器微型化的目的,在已有Hspice磁通门探头信号产生模型的基础上,提出一种由双2阶模块级联的开关电容带通滤波器实现选频放大功能的方法,...     

换路定理及其特殊情形

本文详尽地说明了换路定理与基尔霍夫定律和能量守恒定理的关系,以及在特殊情形下如何使用换路定理.1换路定理与基尔霍夫定律的关系换路定理的基本定义是“在换路前(t=0_-)和换路后(t=0_+),线圈的磁链不变[(?)(0_)=(?)(0_+)],电容的电荷不变[Q(0_-)=Q(0_+)]”.因为如果(?)或Qc突变,则u_L=d(?)/dt或i_c=dQ/dt     

非线性介观电路的量子效应

将非线性双向二极管引入介观电路,对非线性介观电路进行量子力学处理.研究表明:由于非线性双向二极管的影响,使得在非线性介观电路可以实现克尔态的制备.并且对克尔态下非线性介观电路的电荷和磁通的量子涨落进行了计算.计算结果表明:两者随时间存在周期性的压缩现象.     

SK8050S特性及其实验研究

SK8050S是由Sanken公司生产的5V他励开关稳压芯片。详细介绍了SK8050S的电气特性并对其工作效率和稳压性等主要参数进行了实验研究。文中给出了具体的实验电路和测试方法，实验结果表明SK8050S在工作效率和稳压性方面远远超过目前通常使用的三端稳压器L7805，能够输出高达3A的电流且电压稳定在5V。效率可高达91％。     

Optimization of word-line booster circuits for low-voltage flashmemories

Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one of more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed     

High-Frequency Resonant Transistor DC-DC Converters

Transistor dc-dc converters which employ a resonant circuit are described. A resonant circuit is driven with square waves of current or voltage, and by adjusting the frequency around the resonant point, the voltage on the resonant components can be adjusted to any practical voltage level. By rectifying the voltage across the resonant elements, a dc voltage is obtained which can be either higher or lower than the input dc voltage to the converter. Thus, the converter can operate in either the step-up or step-down mode. In addition, the switching losses in the inverter devices and rectifiers are extremely low due to the sine waves that occur from the use of a resonant circuit (as opposed to square waves in a conventional converter); also, easier EMI filtering should result. In the voltage input version, the converter is able to use the parasitic diode associated with an FET or monolithic Darlington, while in the current input version, the converter needs the inverse blocking capability which can be obtained with an IGT or GTO device. A low-power breadboard operating at 200-300 kHz has been built. Two typical application areas are switching power supplies and battery chargers. The converter circuits offer improvements over conventional circuits due to their high efficiency (low switching losses), small reactive components (high-frequency operation), and their step-up/stepdown ability.     

Hybrid mode-switched control of DC-DC boost converter circuits

This paper has proposed a new switching scheme for controlling dc-dc boost converter circuits. The converter is represented as a hybrid system with three modes of operation. The switching among these modes is governed by the adjustable reference voltage and a reference current which are calculated by an energy balance principle. The scheme has been applied to a realistic converter circuit modeled with various parasitic components. All the specifications related to the ripple voltage, line and load regulation are shown to be achievable by relating them to the switching surfaces, namely a reference voltage and a reference current. The state trajectories have been shown to reach a hybrid limit cycle already proved to be super-stable from consideration of chaos. Numerical results clearly bring out the advantages of the proposed control scheme.     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

The tetrode power transistor

Power transistor circuits are characterized by the fact that the collector current must swing over a wide range of values during any complete cycle of operation. One disadvantage of present-day alloyed junction power transistors is that the current gain decreases with increasing collector current. This causes distortion in linear applications and makes temperature stabilization in switching circuits more difficult. Power transistors having emitter areas large enough to handle currents in the amperes range can be made as tetrodes by use of an annular ring geometry. Experimental results show that the gain characteristics can be altered by applying a bias voltage or a portion of the signal voltage transversely across the base. The gain characteristic can be made flatter for improved fidelity in audio applications, or even reversed to give increasing gain with collector current for certain switching applications. Practical circuitry utilizing the improved gain characteristics of power tetrodes has been developed, and the annular geometry permits the fabrication of tetrodes using conventional alloying techniques.     

一种新型软开关DC-DC PWM升压变换器设计

为提高转换效率并降低电源开关的电流应力,提出一种基于新型有源缓冲电路的PWM DC-DC升压变换器。该有源缓冲电路使用ZVT—ZCT软开关技术,分别提供了总开关ZVT开启及ZCT闭合、辅助开关ZCS开启及ZCT闭合。消除了总开关额外的电流及电压应力,消除了辅助开关电压应力,且有源缓冲电路的耦合电感降低了电流应力。另外,通过连续将二极管添加到辅助开关电路,防止来自共振电路的输入电流应力进入总开关。实验结果表明,相比传统的PWM变换器,新的DC-DC PWM升压变换器在满负荷时电流应力降低且总体效率能达到98.7%。     

Bidirectional DC resonant converter with magnetic-coupling current balance

This paper studied a bidirectional frequency-control dc converter with magnetic-coupling to achieve 1) current balance on low voltage side, 2) low switching losses on power devices, and 3) bidirectional power transfer capability. The developed circuit is basically constructed by half-bridge circuits on input and output sides. LLC resonant tank with frequency-control is used to obtain low switching losses on power devices. Magnetic-coupling element is used to achieve current balance on low voltage side. Synchronous rectifiers are employed on low voltage and high current side to decrease power losses and increase circuit efficiency. The effectiveness of the studied circuit is verified from a 720 W laboratory prototype.     

Reducing IGBT losses in ZCS series resonant converters

The fundamental operational parameter that controls the losses in series resonant power converters was found to be the reflected DC voltage transfer ratio. Losses which are a function of the average current (such as conduction losses of insulated gate bipolar transistors and diodes) are independent of the switching frequency. Losses which are associated with the RMS current are a function of both the reflected DC voltage ratio and the switching frequency ratio. Universal and normalized graphs, derived in this paper, can be conveniently used to assess the expected RMS and average current conduction losses under any given operational conditions. The residual switching losses in zero-current-switching series resonant power converters operating in continuous current mode can be reduced by simple current snubbers placed in the commutation circuits. The experimental results of this paper confirm the theoretical predictions and demonstrate that the turn-on snubbers can reduce switching losses by about 1.5% at a switching frequency of 65 kHz     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively