基于受激布里渊散射的40 Gb/s时钟提取试验

对基于受激布里渊散射效应(SBS)的时钟恢复系统模型进行了试验验证,实现了40 Gb/s载波抑止归零码(CSRZ)的全光时钟提取.试验结果表明由于产生了强烈的受激布里渊散射的梳状放大特性,光信号的时钟分量得到显著增强.在不改变该模型结构的基础上,利用G.652普通单模光纤传输8 km而不经过色散补偿的40 Gb/s载波抑止归零码光信号恶化以后仍可进行良好地时钟恢复,时钟抖动小于6.5 ps.研究证明该方案可在一定程度上抵制传输信号恶化所造成的影响,并无明显的码型效应,适合高速长距离全光时钟提取.     

采用单调制器实现载波抑制归零码的研究

文章对基于电模拟转换开关和混频器的采用单调制器产生载波抑制归零(CSRZ)码的方案进行了理论分析,提出了一种基于预编码器的简单、易集成的单调制器生成CSRZ码的方法,仿真验证了该方法生成的CSRZ码与传统方法产生的CSRZ码相比具有更窄的调制谱宽(约15 GHz)和更强的色散容纳能力(可达±1 320 ps/nm).     

恶化非归零码信号的全光时钟恢复

全光时钟提取结构应对输入信号的恶化程度有一定的容忍度.在一种半导体光放大器(SOA) 啁啾光纤布拉格光栅(CFBG) 受激布里渊散射(SBS)的方式实现非归零(NRZ)码信号的全光时钟提取结构中,半导体光放大器和啁啾光纤布拉格光栅共同作用实现了非归零码信号的时钟分量增强,基于受激布里渊散射的全光时钟提取结构提取出非归零码的光时钟信号.实验通过对不同恶化程度的非归零码信号的时钟提取比较发现,恶化信号的信噪比是影响光时钟提取的关键.输入非归零码信号的信噪比越差,光时钟信号光谱的噪声水平越高,提取出的光时钟信号的幅度越低.当时钟增强非归零码信号的时钟数据抑制比低于-10 dB时,无法实现非归零码信号的时钟提取.     

NRZ码和CSRZ码在40 Gbit/s单通道系统中传输性能分析

文章仿真了非归零码(NRZ)和载波抑制归零码(CSRZ)在40 Gbit/s单通道系统中G.652光纤上传输6×80 km的性能.比较了两种码型对接收端光滤波器和电滤波器带宽的要求、不同的入纤功率下功率代价以及残余色散对比.结果表明,在高速传输系统中,CSRZ码的传输性能明显优于NRZ码.     

不同调制码型的偏振模色散补偿研究

在40Gb/s的光纤通信系统中,用三段模拟器模拟光纤传输中的一阶与二阶偏振模色散(PMD),采用单偏振态的偏振度(DOP)作为多级PMD补偿器的反馈信号,对归零(RZ)码、非归零(NRZ)码、载波抑制归零(CSRZ)码和啁啾归零(CRZ)码分别进行四个自由度的一级、六个自由度的二级和十个自由度的三级PMD补偿器的补偿.仿真得到了四种码型的DOP与误码率(BER)的关系,同时补偿后的BER、DOP和PMD的变化关系表明,对RZ和NRZ码采用二级补偿器的效果比一级和三级补偿器要好得多,对CSRZ码和CRZ码采用单偏振态的DOP作为反馈信号进行PMD补偿的效果并不理想.     

偏振相关损耗对偏振模色散补偿系统性能的影响

数值分析了40Gb／s占空比50％的归零码（RZ）、占空比38％的RZ和载波抑制归零码（CSRZ）3种不同码型系统中偏振相关损耗（PDL）对偏振模色散（PMD）补偿的性能，并和不考虑PDL的情况作了比较。结果表明，由于PDL的存在，导致补偿系统的补偿性能恶化严重，使得损耗概率增加，眼图张开度减小；3种码型中，CSRZ码型系统的缓解性能比其他两种码型要好。     

采用滤波技术提高不同码型差分群时延动态范围研究

采用宽带滤波、窄带滤波和非对称滤波3种滤波技术,将其分别应用于归零码（RZ）、载波制RZ（CSRZ）、差分相移键控RZ（RZ-DPSK）和差分相移钯控的载波抑制RZ（CSRZ—DPSK）4种不同码型的系统中,数值模拟结果表明,滤波技术确能提高差分群时延（DGD）的监控范围;在3种滤波技术中,以窄带滤波技术适合每种码型并使用DGD响应范围最大而具有更好的优势。实验验证了滤波技术提高DGD响应范围的有效性。     

不同编码技术在40Gb/s光纤通信中的应用研究

介绍了利用马赫-曾德尔调制器产生NRZ码、Rz码及CSRZ码三种码型的基本原理,并对比分析了其色散和非线性容限大小,在此基础上基于光二进制差分相移键控(oDPSK)调制技术,在40Gb/s通信系统中对结果进行了光纤链路仿真验证.结果表明,CSRZ-DPSK具有较高的色散容限和非线性容限,是未来长距离高速光纤通信中最具优...     

基于高精细度F-P滤波器的40Gb/s全光时钟提取

提出了一种基于高精细度Fabry-Perot(F-P)滤波器的全光时钟提取方案,并进行了实验验证。为了实现对信号波长无关的特性,系统利用光纤中交叉相位调制(XPM)效应对输入信号进行正码波长变换,使变换后的波长始终与F-P滤波器的透射峰精确对准。采用精细度为1 012的高精细度F-P滤波器提取时钟,并利用半导体光放大器(SDA)的自增益调制(SGM)效应进一步抑制时钟信号的低频噪声,保证了高质量的时钟输出。实验中,利用这种装置对40 Gb/s归零(RZ)码信号进行了时钟提取,得到了抖动为285 fs的高质量40 GHz时钟信号,验证了方案的可行性。     

40Gb/s CSRZ-RZ信号波长与调制格式转换的研究

通过利用高非线性光子晶体光纤的交叉偏振调制效应,在60m的高非线性光子晶体光纤中实现了40Gb/s的载波抑制归零(carrier-suppressed return-to-zero CSRZ)信号的波长变换和载波抑制归零码(CSRZ)到归零码(return-to-zero RZ)的调制格式变换,并通过理论计算分析了走离...     

Chromatic Dispersion Monitoring of CSRZ Signal for Optimum Compensation Using Extracted Clock‐Frequency Component

This paper presents a chromatic dispersion monitoring technique using a clock‐frequency component for carrier‐suppressed return‐to‐zero (CSRZ) signal. The clock‐frequency component is extracted by a clock‐extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high‐speed optical communication systems.     

RZ、CSRZ码在CBG色散补偿系统中的传输

全部利用线性啁啾光纤布拉格光栅（CBG）作色散补偿模块和在线通道滤波顺，在2500km超长距离的G．652光纤上实现10Ghps归零码（RZ）、载波抑制归零码（CSRZ）光信号的无电中继传输，并在2080km和2560km处分别对2种信号的传输性能进行了测试。CSRZ在上述2处的功率代价分别为～1dBm和～3dBm（BER-10^12，PRBS=10^23-1），RZ的功率代价分别为～3dBm和～5dBm，验证了在相同系统平台下CSRZ光信号比RZ光信号有更好的性能.     

Demonstration of CSRZ Signal Generator Using Single‐Stage Mach‐Zehnder Modulator and Wideband CMOS Signal Mixer

In this paper, we demonstrate an electrically band‐limited carrier‐suppressed return‐to‐zero (EB‐CSRZ) signal generator operating up to a 10 Gbps data rate comprising a single‐stage Mach‐Zehnder modulator and a wideband signal mixer. The wideband signal mixer comprises inverter stages, a mixing stage, and a gain amplifier. It is implemented by using a 0.13 μm CMOS technology. Its transmission response shows a frequency range from DC to 6.4 GHz, and the isolation response between data and clock signals is about 21 dB at 6.4 GHz. Experimental results show optical spectral narrowing due to incorporating an electrical band‐limiting filter and some waveform distortion due to bandwidth limitation by the filter. At 10 Gbps transmission, the chromatic dispersion tolerance of the EB‐CSRZ signal is better than that of NRZ‐modulated signal in single‐mode fiber.     

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. In the TSMC 0.25-$mu$m CMOS technology, we implemented 1024 proposed energy recovery clocked flip-flops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. Simulation results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. Using a sinusoidal clock signal for energy recovery prevents application of existing clock gating solutions. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000 $times$ in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two pipelined multipliers one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured. Based on measurement results, the energy recovery clocking scheme and flip-flops show a power reduction of 71% on the clock-tree and 39% on flip-flops, resulting in an overall power savings of 25% for the multiplier chip.      

Dynamics of all-optical clock recovery using two-section index- and gain-coupled DFB lasers

The dynamics of coherent clock recovery (CR) using self-pulsing two-section distributed feedback (TS-DFB) lasers have been investigated. Both simulation and experimental results indicate fast lockup and walk-off of the clock-recovery process on the order of nanoseconds. Phase stability of the recovered clock from a pseudorandom bit sequence (PRBS) signal can be achieved by limiting the detuning between the frequency of free-running self-pulsation and the input bit rate. The simulation results show that all-optical clock recovery using TS-DFB lasers can maintain a better than 5% clock phase stability for large variations in power, bit rate, and optical carrier frequency of the input data and therefore is suitable for applications in optical packet switching.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

钟控准静态能量回收逻辑电路

钟控准静态能量回收逻辑 (clocked quasi- static energy recovery logic,CQSERL)只在输入信号导致输出状态发生变化的情况下才对电路节点充电 (或者回收 ) ,不需要在每个功率时钟周期循环充电和回收操作 ;CQSERL是单端输入输出逻辑 ,减小了电路实现代价 .设计了 4位 QSERL 串行进位加法器 (RCA)电路 ,和相应的 CMOS电路进行了功耗比较 .功率时钟为 10 MHz时 ,CQSERL 电路功耗是对应 CMOS电路的 35 % .流片实现了一个简单结构的正弦功率时钟产生电路 ,功率时钟的频率和相位与外接系统时钟相同     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.