Limited yield estimation for visual defect sources

Although kill rate, kill ratio, and limited yield for visual defects are useful concepts in yield management, the formal definitions of these concepts, how to estimate them, especially in the presence of inspection error, and assumptions necessary for their application, are lacking in the literature. The concept of limited yield as the effect of a visual defect source on overall yield of a process is formally derived and the product of the individual limited yields for the visual defect sources is shown to equal the overall yield of the process. As a result of a more rigorous definition of limited yield, a major simplification in the calculation of limited yield over other methods is obtained. Basic to the notion of limited yield are the concepts of kill rate and kill ratio. The kill rate expresses how likely it is that a die with a certain visual defect will be rejected at probe. The kill ratio is shown to be the increased chance, relative to the baseline yield, of a die being rejected when a particular visual defect type is present. The limited yield concept is discussed and illustrated with a practical example using semiconductor visual defect data     

Methods to Quantify the Detection Probability of Killing Defects

Two methods are presented to quantify the killing defect detection probability, or capture rate, of inline defect inspections. The first method uses yield impact and kill ratio of defects above a given size. By comparing the theoretical, critical-area based dependence between the yield impact and the kill ratio of defects above a given size, with the dependence as found from defect–yield correlation on product wafers, an estimate can be made of the fraction of yield impact explained by detected defects. The second method uses conventional defect–yield correlation. By plotting wafer level yield of clean die against the yield impact found by defect–yield correlation, it is possible to estimate the yield impact of undetected defects.     

In-line defect sampling methodology in yield management: anintegrated framework

In this paper we provide an integrated framework for designing the optimal defect sampling strategy for wafer inspection, which is crucial in yield management of state-of-the-art technologies. We present a comprehensive cost-based methodology which allows us to achieve the trade-off between the cost of inspection and the cost of yield impact of the undetected defects. We illustrate the effectiveness of our methodology using data from several leading fablines across the world. We demonstrate that this work has already caused a significant change in the sampling practices in these fablines especially in the area of defect data preprocessing (declustering), in-line defect based yield prediction, and optimization of wafer inspection equipment allocation     

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

Fast extraction of defect size distribution using a single layershort flow NEST structure

Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield     

Modeling of real defect outlines and parameter extraction using acheckerboard test structure to localize defects

For efficient yield prediction and inductive fault analysis, it is usually assumed that defects have the shape of circular discs or squares. Real defects, however, exhibit a great variety of different shapes. This paper presents a more accurate model. The defect outline is approximated by an ellipse, and an equivalent circular defect is determined that causes a fault with the same probability as the real defect. To utilize this model, only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a novel test structure design. The checkerboard test structure uses the boundary pad frame of standard chips and thus achieves a large defect sensitive area. This area is partitioned into many small regions that can be analyzed separately. Defects are localized by simple electrical measurements. This allows an efficient optical inspection that can provide detailed information about the detected defects     

Correlation between predicted cause of SRAM failures and in-line defect data

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.     

Micromasking of plasma etching due to bacteria: a yield detractorfor ULSI

Continued size reduction of semiconductor microelectronic circuits increases their sensitivity to ultra small particulate contaminants. A form of self-replicating particulate is bacteria found in ultrapure water systems. The bacteria can micromask plasma etches causing electrical shorts between adjacent conduction paths, thereby providing a key yield loss mechanism when fabricating high density circuits. This paper discusses defects caused by water born bacteria in tight pitch repetitive patterns found in high density memory circuits. Using high resolution wafer inspection tools and scanning electron microscopy, intentionally introduced bacteria were located on wafers before plasma etching and the same locations were inspected after the etch was completed. While in some cases the defect formed followed the bacteria shape, in many instances the post-etch defects did not resemble the original bacteria in any way. Besides electrical shorts between conducting regions, due to the specifics of the technology, defects due to bacteria micromasking of dry etches can also cause failures between two layers of polysilicon. The “before” and “after” data provided by this work present a means of identifying a key defect source, namely bacteria, based on defect appearance     

Efficient macromodeling of defect propagation/growth mechanisms inVLSI fabrication

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material, and the underlying IC topography. An efficient defect macromodeling methodology based on the rigorous two-dimensional (2-D) topography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size, and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with the data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy for our method of developing contamination to defect propagation/growth macromodels     

A unified yield model incorporating both defect and parametriceffects

A new approach to modeling yield is presented, which inherently includes both the effects of the conventional defect contributors and the parametric yield loss contributors often treated separately in existing yield models. These parametric yield losses are particularly important during the startup yield-improvement phase of new technology introduction, in many performance-sensitive products such as analog devices and high-speed digital devices, and in analyses of bin-split yields. By assuming a distribution in the size of defects, from point defects up to defects as large as or larger than a wafer, the parametric yield contributors can be viewed as simply rather large, design-dependent defects, which will render IC's unacceptable if any portion of the large defect overlaps the defect-sensitive area of a chip. In this way, the conventional Poisson model, or various extensions of the well-known Murphy model, can be augmented in a straightforward and general way to include parametric yield loss. It is shown that parametric yield losses introduce an additional die size dependence for yield that can help to account for the observed dependence of yield on die area. The model is compared to other models and to experimental yield data to illustrate both its utility in separating yield contributors and its close agreement with experimental yield data     

Mirror electron microscope for inspecting nanometer-sized defects in magnetic media

We developed a mirror electron microscope (MEM) for the highly sensitive inspection of defects on the magnetic storage disks of commercial hard disk drives (HDDs). Magnetic fields recorded on a magnetic disk do not affect the MEM images for inspection. We used artificial defects in a detection sensitivity evaluation to test the effectiveness of our MEM inspection tool and found that it was sensitive enough to detect defects that were 67 nm in diameter and 7 nm in height. The size of a MEM image for a defect was eight times larger than the physical size measured by an atomic force microscope. The obtained sensitivity is beyond the resolution power of the objective lens of the MEM itself. This is because MEM images the distortion of static electrical potentials spread over a larger area than the physical size of a defect itself and the image is obtained in out-of-focus condition of an objective lens. The image acquisition time was 50 ms, which corresponded to the inspection time of 4 h for the full surface inspection of a 2.5 in. magnetic disk. MEM is a promising technique for conducting a highly sensitive defect inspection and a high throughput inspection simultaneously as compared with an SEM-based inspection.     

Microelectronic test structures for rapid automated contactlessinline defect inspection

Simple but unique and space-saving microelectronic test structures were designed to afford automated inline contactless defect inspection in a Scanning Electron Microscope (SEM)-voltage contrast (VC) mode for rapid electrical defect-monitoring, along with in situ defect-isolation and characterization capabilities. Such an automated inspection can support accelerated yield learning through increased defect-learning cycles, particularly on the sub-0.25-μm-rule designs, as defects below optical resolution become significant. The system is also capable of the traditional visual inspection in the high-energy secondary-electron emission mode, affording the accurate determination of the “transfer coefficients” between the optical inspection results and the electrical faults from the SEM-VC inspection, needed for any foreign-material or contamination-to-yield model with high correlation or at a high confidence level     

Facing the defect characterization and localization challenges of bridge defects on a submicronic technology (45 nm and below)

For very deep submicron technologies, 45 nm and less, bridge defects are getting more and more complex and critical. In order to find the exact root cause, accurate defect localization, precise understanding on the nature of the defect and its impact on the fine electrical behaviour of the device are mandatory. At these ultimate technologic nodes, failure analysis techniques show a real lack of efficiency on bridge defect localization while this precise location is one of the keys to find the defect root cause that allows correct implementation of corrective actions to improve yield and reliability.To face this challenge we have built a complete set of signatures related to advance Eldo simulations, performed measurement with ultimate failure analysis tools, fully characterized a microelectronic structure in advanced technology presenting a bridge defect and established a complete link between all these data and the failure location.     

Systematic defect improvement integration of dual damascene processes development on nano semiconductor fabrication

Process defects of semiconductor wafer nanotechnology manufacturing process can often impact product yields, depending on the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. Manufacturing process-induced defects prevention should begin with an assessment of the critical risks associated with the wafer fabrications. Systematic identification and classification approaches have been introduced to improve the process yield by defects sampling and images reviewing. This study presents comprehensive investigation of a process defects monitor and integration on semiconductor copper manufacturing process and technology, and module process integration of the problem of defects reduction on semiconductor manufacturing processes. Experiments on electrical devices were performed to identify the defect source and determine the mechanism of defect formation, and integrated manufacturing processes implemented to eliminate defect issues are also investigated.     

Harp test structure to electrically determine size distributions ofkiller defects

To improve accuracy of electrically based measurements of defect densities and defect size distributions, we present a novel harp test structure (HTS). There, horizontal and vertical parallel lines will be placed inside a given boundary pad frame without using any additional active semiconductor devices. The enhanced two-dimensional (2D) permutation sequence provides that all neighborhood relationships of adjacent test structure lines are unique. This is the key to disentangle even multiple faults detected by fast digital measurements. For this reason, the number and size of individual defects will be extracted anywhere inside or in-between layers. Experimental results show, that not only optical measurements, but also electrical measurements at a harp test structure are sufficient to get a precise defect size distribution that enables size distribution modeling for yield prediction     

METRO-3D: an efficient three-dimensional wafer inspection simulator for next-generation lithography

Wafer inspection schemes for next-generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of deep ultraviolet (DUV) wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning, or full-field schemes can be extremely costly; therefore, simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional (3-D) simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a 3-D simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. We will present simulation results from METRO-3D for various wafer inspection schemes, including high NA schemes, on NGL topographies with highly absorptive materials.     

Actinic inspection of EUVL mask blank defects by photoemission electron microscopy: Effect of inspection wavelength variation

Extreme ultraviolet (EUV) photoemission electron microscopy (PEEM), which employs standing wave field illumination of a sample, is a potential tool for at-wavelength inspection of phase defects on extreme ultraviolet lithography (EUVL) mask blank. In this paper, we will demonstrate that the contrast of an underneath multilayer programmed defect in EUV-PEEM image is strongly dependent on the inspection wavelength. The observed contrast variation at different inspection wavelengths is in good agreement with the simulation result of a standing wave field on surface of multilayer stack in the mask blank sample. We also observed some native defects on the programmed defect sample, and found that some of them reverse their contrast with varying inspection wavelengths while others do not.     

Burn-in effect on yield

By removing infant mortalities, burn-in of semiconductor devices improves reliability. However, burn-in may affect the yield of semiconductor devices since defects grow during burn-in and some of them end up with yield loss. The amount of yield loss depends upon burn-in environments. Another burn-in effect is the yield gain. Since yield is a function of defect density, if some defects are detected and removed during burn-in, the yield of the post-burn-in process can be expected to increase. The amount of yield gain depends upon the number of defects removed during burn-in. In this paper we present yield loss and gain expressions and relate them with the reliability projection of semiconductor devices in order to determine burn-in time     

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication—optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron-beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper.     

消除产品良率隐藏的杀手--电子束检查是铜逻辑和晶圆代工厂的最佳方法

监控和消除隐藏的电路缺陷已成为130nm和130nm以下器件的关键。这使得电子束检查正在广泛应用于开发、试生产和量产的监控过程。我们将描述当前铜逻辑和晶圆代工厂电子束检查技术的执行情况,其中包括详细的案例研究,它说明了从开发到量产过程中应用电子束检查技术的好处。我们也描述了过去克服通用工具障碍的方法。然后,分别介绍了利用电子束检查技术的新进展,以及为假设的20000WSPMφ300mm工厂模拟的最理想执行情况的最佳实例。