Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

A new two-mode channel FET (TMT) for super-low-noise and high-powerapplications

A super-low-noise two-mode channel FET (TMT) with high- and plateau-shaped transconductance (g_m) characteristics has been developed. It has two electron transport modes against the applied gate voltage (V_gs). That is, the electrons mainly drift in a highly doped channel region at a shallow V_gs. A plateau g_m region and the maximum g_m were achieved at a V_gs range of -0.25~+0.5 V and 535 mS/mm, respectively. The minimum noise figure and associated gain for the TMT were superior in the low-drain-current (I_ds) region and nearly equal in the middle and high I_ds region to those of an AlGaAs/InGaAs pseudomorphic HEMT fabricated using the same wafer process and device geometry     

Detection of the trapped electron distribution of PMOSFET's afterhot-carrier stress

A method of obtaining the spatial distribution of hot-carrier-induced trapped electrons in the gate oxide (N_0t(x)) of PMOSFETs is introduced with the aid of a two-dimensional simulator. The measured I_ds versus V_ds for various V_gs for low drain bias and I_ds versus V_gs have been compared with data obtained from the simulation concerning the obtained spatial distribution of trapped electrons in the gate oxide. There exists a high degree of agreement between the measured current-voltage characteristics after hot-carrier stress and the simulation results concerning the newly obtained spatial distribution of trapped electrons in the gate oxide     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

Improved hot-carrier immunity in submicrometer MOSFETs withreoxidized nitrided oxides prepared by rapid thermal processing

The fabrication of 0.8-μm MOSFETs using 7.7-nm-thick nitrided oxides reoxidized by rapid thermal processing at 900-1150°C for 15-200 s is described. The hot-carrier-induced degradation was studied in terms of subthreshold swing, threshold voltage V_T, and transconductance g_m voltage characteristics. Results indicate that rapid reoxidation markedly improves hot-carrier immunity; lifetimes reaching 30-mV V _T shift and 10 percent g_m degradation are improved by 3 and 1.5 orders of magnitude compared with those for thermal oxides, respectively. A degradation characteristic inherent to the (reoxidized) nitrided-oxide system is found, based on the gate-voltage dependence of g_m degradation     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Channel hot-carrier stressing of reoxidized nitrided silicondioxide

The mechanisms of channel hot-carrier-induced degradation in short n-channel MOSFETs with reoxidized nitrided oxide as the gate dielectric are discussed. Charge pumping measurements, supported by observations on the gate voltage dependence of degradation and the power law dependence of Δg_m on stress time, demonstrate that virtually no interface trap generation occurs in reoxidized nitrided oxides and that electron trapping is the dominant degradation mechanism. Although electron trapping can be enhanced in these dielectrics, this mechanism is not as important for device degradation as interface trap generation, and the net effect is substantially improved resistance to hot-carrier stress. A three-orders-of-magnitude improvement in device lifetime (versus conventional oxide) is demonstrated     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Low-power performance of 0.5-μm JFET for low-cost MMIC's inpersonal communications

The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V_th=0.3 V achieved a maximum DC transconductance of g_m=489 mS/mm at V _ds=1.5 V and I_ds=18 mA. Operating at 0.5 mW of power with V_ds=0.5 V and I_ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F_min=1.2 dB and the average associated gain was G_a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications     

A coupled study by floating-gate and charge-pumping techniques ofhot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V_d/8 to V_d) by hot-hole and/or hot-electron injections, and their generation rates (10^-9 and 10^-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I_d-V_g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I _d-V_g degradation     

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V_th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V_th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V_th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

Charge control, DC, and RF performance of a 0.35-μmpseudomorphic AlGaAs/InGaAs modulation-doped field-effecttransistor

The authors describe a study of charge control in conjunction with DC and RF performance of 0.35-μm-gate-length pseudomorphic AlGaAs/InGaAs MODFETs. Using C-V measurements, they estimate that a two-dimensional electron gas (2DEG) with density as high as 1.0×10¹² cm^-2 can be accumulated in the InGaAs channel at 77 K before the gate begins to modulate parasitic charges in the AlGaAs. This improvement in charge control of about 10-30% over a typical AlGaAs/GaAs MODFET may partially be responsible for the superior DC and RF performance of the AlGaAs/InGaAs MODFET. At room temperature, the devices give a maximum DC voltage gain g _m/g_d of 32 and a current gain cutoff frequency f_T of 46 GHz. These results are state of the art for MODFETs of similar gate length     

Low-frequency noise characteristics of lattice-matched(x=0.53) and strained (x>0.53) In0.52Al0.48As/InxGa1-xAs HEMT's

Extensive bias-dependent and temperature-dependent low-frequency (LF) noise measurements were performed on lattice-matched and strained In_0.52Al_0.48As/In_xGa_1-x As(0.53<x<0.70) HEMTs. The input-noise voltage spectra density is insensitive to V_DS bias and shows a minimum at V_GS corresponding to the peak g_m condition. The corresponding output-noise voltage spectral density, which depends strongly on the gain of the devices, increases with V_DS. The input noise was rather insensitive to indium (In) content. Temperature-dependent low-frequency noise measurements on these devices reveal shallow traps with energies of 0.11, 0.15, and 0.18 eV for 60%, 65%, and 70% In HEMTs. Noise transition frequencies for these devices were on the order of 200-300 MHz and remain almost the same for different channel In content and V_DS bias     

Recombination current in forward-biased p-n junctions

An analytical expression for the recombination current in a forward-biased p-n junction is derived and it is shown that formulas given for the recombination current in most textbooks overestimate the recombination current by a large factor of the order of (V_bi-V)/V_th where V _bi is the built-in voltage, V is the applied forward-bias voltage, and V_th is the thermal voltage     

Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

The effect of channel hot-carrier stressing on gate-oxide integrityin MOSFETs

The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV_T and ΔI _D) have become intolerably degraded. In the extreme cases of stressing at V_G≈V_T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism     

A simple characterization method for silicon-on-insulator materialsusing a depletion-mode MOSFET

A simple method is proposed for extracting the electrical parameters of a silicon-on-insulator (SOI) material from a depletion-mode MOSFET. It is based on an analysis of static input current-voltage I_D(V_G) and transconductance-voltage g_m(V_G) characteristics in the linear region. Functions varying linearly with gate voltage are constructed from I_D(V_G) and g_m(V_G) functions. These new functions allow a straightforward determination of the parameters usually obtained from a capacitance-voltage measurement (doping level, oxide charge, etc.) and also the bulk-layer and accumulation-layer carrier mobility