A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps     

基于40 nm CMOS工艺的毫米波注入锁定分频器

设计了一款应用于60 GHz频率综合器的二分频注入锁定分频器。通过优化射频注入和直流偏置网络,降低了注入信号损耗,提高了注入效率;通过优化注入管和交叉管尺寸、减小寄生电容、降低振荡摆幅,提高了注入效率,降低了功耗;电磁仿真毫米波段电感,建立集总等效电路模型,实现了高感值、低串联电阻的差分电感的设计,提高了锁定范围。电路设计采用SMIC 40 nm 1P6M RF CMOS工艺,芯片核心面积为0.016 mm²。仿真结果表明,在0.8 V电源电压下,电路功耗为5.5 mW,工作频率范围为55.2~61.2 GHz,注入锁定范围为6.0 GHz,满足低功耗和宽锁定范围的要求,适用于毫米波段锁相环频率综合器。     

基于90 nm CMOS工艺的37 GHz分频器

对高速分频器的注入锁定特性进行了研究,并实现了一个基于电流模逻辑的分频器。该分频器采用了电感峰值技术,分频范围可达25~37.3 GHz,电源电压为1.2 V,功耗为24 mW。芯片采用TSMC 90 nm CMOS工艺设计制造,并给出了测试结果。     

一种宽锁定范围的毫米波注入锁定分频器

基于GF 65 nm CMOS工艺,实现了一种宽锁定范围的毫米波注入锁定(IL)分频器。采用电流复用前置放大器和双端混频,有效扩大了分频器的锁定范围,并且不产生额外的功耗。电路仿真结果表明,当调节电压在0~1.2 V变化时,输入频率的锁定范围为81~110 GHz。工作电压为0.8 V时,电路的功耗为5.74 mW。该分频器适用于75~110 GHz的W-band系统。     

Sub-nH Inductor Modeling and Design in 90-nm CMOS Technology for Millimeter-Wave Applications

Inductor design is an important issue in millimeter-wave CMOS circuits. In these frequencies the required inductance is very small and hence special structure is required for inductors. The quality factor is the most important design parameter for these inductors, especially in CMOS process. To incorporate these inductors in circuit simulation, a simple lumped model is necessary. This work proposes a simple and accurate model, developed for design and optimization of such inductors. This model is based on quasi-transverse-electromagnetic-mode assumption. To increase the model accuracy we have separately modeled the short-end section of the inductor. Model parameters are calculated using reported analytic equations and some new empirical equations. Using this model we have designed and optimized a 250-pH inductor with different shield layers, for STMicroelectronics 90-nm digital CMOS process. The accuracy of the model parameters and the evaluation of the model has been carried out using 2-D and method-of-momentss electromagnetic solvers in Advanced Design System, with the substrate modeled using foundry design kit data.     

A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider

A heterodyne receiver performs frequency down-conversion in two steps to relax oscillator and divider speed requirements. The receiver incorporates new concepts such as a current-domain quadrature separation method, a broadband Miller divider based on a passive mixer, and an inductor nesting technique that significantly reduces the length of high-frequency interconnects. Fabricated in 90-nm CMOS technology, the circuit achieves a noise figure of 6.9 to 8.3 dB from 49 GHz to 53 GHz with a gain of 26 to 31.5 dB and I/Q mismatch of 1.6 dB/6.5deg.     

基于90nm CMOS工艺的12GHz二分频器

采用90 nm CMOS工艺,实现了一个基于电流模式逻辑的12 GHz二分频器.该分频器具有很宽的锁定频率范围(1～12 GHz),在输入信号频率为8 GHz时,输入灵敏度达到-30 dBm.分频器工作在1.2 V电源电压下,消耗的电流大约为1.5 mA.给出了该设计的后仿真结果.     

Millimeter-Wave Integrated Circuits in 65-nm CMOS

We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at $+$6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 ${hbox{mm}}^{2}$. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of $+$7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and $+$5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with $-$19 dBm of 1-dB output compression point.      

一种36 GHz CMOS毫米波三倍频器

针对传统三倍频器输出功率和匹配性能差的问题,基于TSMC0.18μm CMOS工艺,提出一种用滤波器作为匹配电路的三倍频器.该三倍频器输出匹配性能好、功率损耗小,提高了三次谐波的输出功率.对晶体管静态特性进行分析,进一步提升输出功率.流片后的实测结果表明,在31.5～36 GHz输出频率范围内,输入功率为0 dBm时,...     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25-mum SOS-CMOS technology, occupies 35times25 mum² and exhibit a operating frequency of 5.6 GHz while consuming 79 muW at a supply voltage of 0.8 V. Process and temperature tolerant operation can be achieved by utilizing a novel compensation circuitry to calibrate the speed of the ring oscillator-based divider. The simple compensation circuitry contains low-speed digital logic and dissipates minimal additional power since it is powered on only during the one-time factory calibration sequence     

A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider

This paper presents the dual-injection-locking technique to enhance the locking range of resonator-based frequency dividers. By fully utilizing the voltage and current injection of the input signal, the divider locking range is extended significantly. The 0.8-mW dual-injection-locked frequency divider was developed in 90-nm digital CMOS technology. The total chip size is 0.77 mm times 0.5 mm. Without any varactor or inductor tuning, the input signal frequency coverage of the divider is from 35.7 to 54.9 GHz. Combined with the excellent locking range and sub-milliwatt power consumption, the figure-of-merit of this work surpasses those of the previous resonator-based dividers by more than one order.     

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS

This brief presents the design and implementation of a high-speed and high-accuracy power-switchable track-and-hold (T/H) in 90-nm CMOS that achieves a total harmonic distortion of $-$ 60 dB at 100 MS/s. With the proposed power-switching (P-S) technique, the T/H amplifier obtains not only further power optimization but also enhanced sampling speed and accuracy. The P-S technique requires no extra voltage headroom in the source-follower amplifier, thus allowing a relatively large input voltage swing of 0.8-$hbox{V}_{rm pp}$ in differential mode. A spurious-free dynamic range of 70 dB at 100 MS/s was measured with an input of 40.6 MHz and 0.8 $hbox{V}_{rm pp}$. While driving a 2.5-pF capacitive load, the T/H consumes 2.97 mW from the 1.2-V supply.      

A CMOS Multi-Phase Injection-Locked Frequency Divider for V-Band Operation

An inductor-less injection-locked frequency divider for high-speed frequency synthesis at V-band is presented. It achieves division by six and operates up to 65 GHz. In addition, it can achieve division ratios of four and two when 44 GHz or 22 GHz input signals are applied, respectively. Implemented in a 0.13 mum digital CMOS technology, the divider draws an average current of 18 mA, and the core area is 0.026 mm² .     

Circuit Techniques for CMOS Divide-By-Four Frequency Divider

This letter describes circuit techniques for obtaining divide-by-four (divide4) frequency dividers (FDs) from CMOS ring-oscillator based injection locked frequency dividers (ILFDs). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. At the supply voltage of 1.8V and at the incident power of 0dBm, for a dual-band ILFD, the divide4 ILFD can provide a locking range of 6.3% from 5.39 to 6.12GHz at low band and 5.9% from 8.84 to 9.38GHz at high band when the dc bias of MOS switches V_inj changes from 0.7 to 1.1V     

90-nm CMOS for microwave power applications

We report, for the first time, the experimental evaluation of a very short channel 90-nm CMOS transistor under RF over-voltage conditions. At 9 GHz and 1.5 V supply a 40 /spl mu/m gate width device is able to deliver 370 mW/mm output power with a PAE of 42% and a transducer power gain of 15 dB. Measurement results at 3 and 6 GHz is also presented. The transistor does not show any degradation in either dc or RF performance after prolonged operation at 1 and 6 dB compression. Simulation show, that the peak voltage, V/sub ds/ at this condition is 3.0 V, while the maximum allowed dc supply voltage is limited by the design rules to 1.2 V. We show for the first time that nanometer-scale CMOS can be used for microwave power applications with severe RF over-voltage conditions without any observable degradation.     

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.     

A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs

This paper describes the design of a pulse-based ultra-wideband (UWB) transmitter for wireless personal area networks (WPANs). The transmitter consists of a pulse generator, a phase-locked loop (PLL), and modulation circuitry. All of the components except the transmit antenna and the reference clock source are integrated. The pulse generator employs on-chip finite-impulse response (FIR) filtering so that the transmitted signal is compliant with the indoor FCC spectral emission limits. The frequency-multiplying PLL is included to provide a stable clock that sets the tap delays of the FIR filter. The transmitter architecture is capable of providing simultaneous binary phase shift keying (BPSK) and pulse position modulation (PPM). Implemented in a 90-nm standard digital CMOS process, the 2.83 mm $^{2}$ prototype transmitter achieves a maximum pulse rate of 1.8 Gpulses/s while dissipating 227 mW from a 1-V supply. The measured jitter at the output of the PLL is 1.9 ${hbox {ps}}_{rm rms}$ and 15.1 ${hbox {ps}}_{rm pp}$.      

A CMOS Direct Injection-Locked Frequency Divider With High Division Ratios

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a $0.18~mu{rm m}$ CMOS process and has a chip core size of $68~mu{rm m}times 70~mu{rm m}$. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.