A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps     

A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider

A heterodyne receiver performs frequency down-conversion in two steps to relax oscillator and divider speed requirements. The receiver incorporates new concepts such as a current-domain quadrature separation method, a broadband Miller divider based on a passive mixer, and an inductor nesting technique that significantly reduces the length of high-frequency interconnects. Fabricated in 90-nm CMOS technology, the circuit achieves a noise figure of 6.9 to 8.3 dB from 49 GHz to 53 GHz with a gain of 26 to 31.5 dB and I/Q mismatch of 1.6 dB/6.5deg.     

Sub-nH Inductor Modeling and Design in 90-nm CMOS Technology for Millimeter-Wave Applications

Inductor design is an important issue in millimeter-wave CMOS circuits. In these frequencies the required inductance is very small and hence special structure is required for inductors. The quality factor is the most important design parameter for these inductors, especially in CMOS process. To incorporate these inductors in circuit simulation, a simple lumped model is necessary. This work proposes a simple and accurate model, developed for design and optimization of such inductors. This model is based on quasi-transverse-electromagnetic-mode assumption. To increase the model accuracy we have separately modeled the short-end section of the inductor. Model parameters are calculated using reported analytic equations and some new empirical equations. Using this model we have designed and optimized a 250-pH inductor with different shield layers, for STMicroelectronics 90-nm digital CMOS process. The accuracy of the model parameters and the evaluation of the model has been carried out using 2-D and method-of-momentss electromagnetic solvers in Advanced Design System, with the substrate modeled using foundry design kit data.     

基于90nm CMOS工艺的12GHz二分频器

采用90 nm CMOS工艺,实现了一个基于电流模式逻辑的12 GHz二分频器.该分频器具有很宽的锁定频率范围(1～12 GHz),在输入信号频率为8 GHz时,输入灵敏度达到-30 dBm.分频器工作在1.2 V电源电压下,消耗的电流大约为1.5 mA.给出了该设计的后仿真结果.     

Millimeter-Wave Integrated Circuits in 65-nm CMOS

We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at $+$6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 ${hbox{mm}}^{2}$. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of $+$7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and $+$5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with $-$19 dBm of 1-dB output compression point.      

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25-mum SOS-CMOS technology, occupies 35times25 mum² and exhibit a operating frequency of 5.6 GHz while consuming 79 muW at a supply voltage of 0.8 V. Process and temperature tolerant operation can be achieved by utilizing a novel compensation circuitry to calibrate the speed of the ring oscillator-based divider. The simple compensation circuitry contains low-speed digital logic and dissipates minimal additional power since it is powered on only during the one-time factory calibration sequence     

A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider

This paper presents the dual-injection-locking technique to enhance the locking range of resonator-based frequency dividers. By fully utilizing the voltage and current injection of the input signal, the divider locking range is extended significantly. The 0.8-mW dual-injection-locked frequency divider was developed in 90-nm digital CMOS technology. The total chip size is 0.77 mm times 0.5 mm. Without any varactor or inductor tuning, the input signal frequency coverage of the divider is from 35.7 to 54.9 GHz. Combined with the excellent locking range and sub-milliwatt power consumption, the figure-of-merit of this work surpasses those of the previous resonator-based dividers by more than one order.     

A CMOS Multi-Phase Injection-Locked Frequency Divider for V-Band Operation

An inductor-less injection-locked frequency divider for high-speed frequency synthesis at V-band is presented. It achieves division by six and operates up to 65 GHz. In addition, it can achieve division ratios of four and two when 44 GHz or 22 GHz input signals are applied, respectively. Implemented in a 0.13 mum digital CMOS technology, the divider draws an average current of 18 mA, and the core area is 0.026 mm² .     

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS

This brief presents the design and implementation of a high-speed and high-accuracy power-switchable track-and-hold (T/H) in 90-nm CMOS that achieves a total harmonic distortion of $-$ 60 dB at 100 MS/s. With the proposed power-switching (P-S) technique, the T/H amplifier obtains not only further power optimization but also enhanced sampling speed and accuracy. The P-S technique requires no extra voltage headroom in the source-follower amplifier, thus allowing a relatively large input voltage swing of 0.8-$hbox{V}_{rm pp}$ in differential mode. A spurious-free dynamic range of 70 dB at 100 MS/s was measured with an input of 40.6 MHz and 0.8 $hbox{V}_{rm pp}$. While driving a 2.5-pF capacitive load, the T/H consumes 2.97 mW from the 1.2-V supply.      

Circuit Techniques for CMOS Divide-By-Four Frequency Divider

This letter describes circuit techniques for obtaining divide-by-four (divide4) frequency dividers (FDs) from CMOS ring-oscillator based injection locked frequency dividers (ILFDs). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. At the supply voltage of 1.8V and at the incident power of 0dBm, for a dual-band ILFD, the divide4 ILFD can provide a locking range of 6.3% from 5.39 to 6.12GHz at low band and 5.9% from 8.84 to 9.38GHz at high band when the dc bias of MOS switches V_inj changes from 0.7 to 1.1V     

90-nm CMOS for microwave power applications

We report, for the first time, the experimental evaluation of a very short channel 90-nm CMOS transistor under RF over-voltage conditions. At 9 GHz and 1.5 V supply a 40 /spl mu/m gate width device is able to deliver 370 mW/mm output power with a PAE of 42% and a transducer power gain of 15 dB. Measurement results at 3 and 6 GHz is also presented. The transistor does not show any degradation in either dc or RF performance after prolonged operation at 1 and 6 dB compression. Simulation show, that the peak voltage, V/sub ds/ at this condition is 3.0 V, while the maximum allowed dc supply voltage is limited by the design rules to 1.2 V. We show for the first time that nanometer-scale CMOS can be used for microwave power applications with severe RF over-voltage conditions without any observable degradation.     

A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider

A high-frequency CMOS injection-locked frequency divider (ILFD) is presented by using the distributed LC, series inductor peaking, and multiple-injection techniques. The theoretical analysis for the aforementioned techniques will be given. This ILFD has been fabricated in a 65-nm CMOS process. The core area is 0.4 mm times 0.36 mm without pads. The measured locking range is from 104 to 112.8 GHz, and its power consumption is 7.2 mW from a supply of 1.2 V.     

A CMOS Direct Injection-Locked Frequency Divider With High Division Ratios

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a $0.18~mu{rm m}$ CMOS process and has a chip core size of $68~mu{rm m}times 70~mu{rm m}$. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.      

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.     

A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs

This paper describes the design of a pulse-based ultra-wideband (UWB) transmitter for wireless personal area networks (WPANs). The transmitter consists of a pulse generator, a phase-locked loop (PLL), and modulation circuitry. All of the components except the transmit antenna and the reference clock source are integrated. The pulse generator employs on-chip finite-impulse response (FIR) filtering so that the transmitted signal is compliant with the indoor FCC spectral emission limits. The frequency-multiplying PLL is included to provide a stable clock that sets the tap delays of the FIR filter. The transmitter architecture is capable of providing simultaneous binary phase shift keying (BPSK) and pulse position modulation (PPM). Implemented in a 90-nm standard digital CMOS process, the 2.83 mm $^{2}$ prototype transmitter achieves a maximum pulse rate of 1.8 Gpulses/s while dissipating 227 mW from a 1-V supply. The measured jitter at the output of the PLL is 1.9 ${hbox {ps}}_{rm rms}$ and 15.1 ${hbox {ps}}_{rm pp}$.      

16GHz CMOS4∶1分频器

采用TSM C 0.18μm标准CM O S工艺实现了一种4∶1分频器。测试结果表明,电源电压1.8 V,核心功耗18 mW。该分频器最高工作频率达到16 GH z。当单端输入信号为-10 dBm时,具有5.8 GH z的工作范围。该分频器可以应用于超高速光纤通信以及其它高速数据传输系统。     

A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-$Omega$ I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-$Omega$ output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5–64.5 GHz, and the measured phase noise penalty is 9.2 $ pm 1~$dB with respect to a 20.2-GHz input. The $0.3times 0.3~ hbox{mm}^{2}$ tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.      

16 GHz CMOS 4:1分频器

采用TSMC 1.18 μm标准CMOS工艺实现了一种4:1分频器.测试结果表明,电源电压1.8 V,核心功耗18 mW.该分频器最高工作频率达到16 GHz.当单端输入信号为-10 dBm时,具有5.8 GHz的工作范围.该分频器可以应用于超高速光纤通信以及其它高速数据传输系统.     

0.18μm CMOS PLL频率综合器中可编程分频器的设计与实现

介绍了用于WLAN802．11a收发信机的PLL频率综合器中可编程分频器的设计。基于ARTISAN标准单元库对可编程分濒器进行了设计，详细介绍了自定义线负载模型、版图规划、时钟树综合、布局布线、静态时序分析等VlSI设计流程．并通过前端和后端设计的相互协作对电路进行了反复优化。最后给出了可编程分频器的后仿真结果、芯片照片和测试结果，芯片内核面积1360．5μm^2，测试结果表明设计符合要求。     

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.