Extended charge-control model for bipolar transistors

In modeling bipolar transistors the charge-control concept provides a means to predict dynamic behavior from a detailed knowledge of the steady state. As such, it is a first-order approximation lacking accuracy. It is shown that a considerable improvement can be obtained when the concept is extended by allowing time delays in the relations between controlling charges and terminal voltages and currents. It suffices to introduce two delays whose magnitudes can be determined or estimated from the steady-state solution. The increased range of validity of the extended charge-control model is demonstrated in detail, by confronting it with a rigorous model and comparing small-signal parameters.     

Circuit representation of the integral charge-control model of bipolar transistors

The integral charge-control model (ICM) of bipolar transistors developed by Gummel and Poon (abstr. B31388 of 1970) describes the device physics compactly, coherently, and more accurately than do the other existing compact models of transistors. The significance of the ICM to circuit analysis is, however, masked by various analytical expressions describing the device physics. This significance is recognized here by developing a circuit representation of the ICM that is topologically the same as that for the Ebers-Moll model.     

Application of a charge-control model to high-voltage power transistors

Basic charge-control concepts are applied to the problem of predicting the static and large-signal switching characteristics of high-voltage transistors, with particular emphasis placed on the quasi-saturation region. Under the assumptions of unity base transport factor and one-dimensional current flow, simple equations for device electrical characteristics are derived in terms of readily determined device parameters. A two-region model is developed for predicting the turn-on process. Measured turn-on waveforms and collector characteristics are compared with the calculated behavior for a BVCE0= 400 V switching transistor. A comparison with hFE(Ic) data is also given for different temperatures. In all cases, good agreement with the predictions of the model is obtained. Implications of the model with respect to device design and characterization are discussed.     

Two-dimensional charge-control model for MODFET's

A dc model for MODFET's accounting for two-dimensional effects is proposed. In this model, charge control is realized by solving the two-dimensional Poisson equation in the depleted AlGaAs region. The transport picture used for the two-dimensional electron gas (2-DEG) in the AlGaAs/GaAs heterojunction relies on the quasi-Fermi level together with a field-dependent mobility and therefore includes 2-DEG diffusion effects. Our approach reduces the analysis to a single integral equation.I-Vcurves, which provide a good fitting to the reported experimental data, are obtained using a smooth velocity-field curve. The channel voltage, 2-DEG concentration, parallel electric-field, and drift velocity along the channel are given in this study and provide a clear picture of current saturation. The model is consistent with the approximate two-region saturation picture but provides a smoother transition. We observe a large diffusion current component along the channel in addition to the drift current. However, the total saturation current obtained has nearly the same value as found from the two-region model. This new model with two-dimensional charge control provides much insight into the current saturation mechanism of the MODFET.     

A new SIMPLORER model for single-electron transistors

In the first part of this paper, we present simulations of single-electron transistor (SET) output characteristic using Maple. Typical SET I–V characteristics and charge energies curves are presented by developing Maple programs. In the second part of this work, we develop a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. Finally, we propose a new bloc using SIMPLORER 7.0 simulator to modulate quantum effects in the SET island. This model is based on a parallel analog–digital converter.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

A charge-control model of the pin diode

A charge-control model of the pin diode is developed which fully accounts for the additional contact-layer storage charges. This part of the storage charge is shown to greatly influence both the forward steady state and the turn-off transient (switching time and transition-loss). Needing limited mathematical efforts, the model seems well suited for analysis of complicated microwave networks with pin diodes, such as phase shifters, limiters, and frequency converters. As is demonstrated by numerical results, an optimal i-layer width may exist for certain applications.     

A new simple analytical emitter model for bipolar transistors

An accurate analytic evaluation of emitter injection into an arbitrarily doped emitter (including a polysilicon-contacted emitter) is presented taking into account position-dependent quantities such as bandgap narrowing, Auger recombination and mobility. Two newly defined dimensionless parameters are introduced that are very useful for emitter design. These parameters are proposed to replace the conventional emitter Gummel number which becomes less useful when appreciable recombination takes place in the emitter. Universal emitter design curves are presented for devices made in silicon, GaAs and InGaAsP or in any other semiconductor for which a newly introduced lifetime model holds good. Numerical simulations show the accuracy and usefulness of the analytical model developed.     

A new model for bipolar transistors at high current

A model for current gain and cutoff frequency falloff at high currents for bipolar transistors is proposed. The model is based on considering that the vertical and lateral base widening occur simultaneously for a typical bipolar transistor. The results of this model successfully fit Pisces-2B simulation results     

Verification of the integral charge-control relation for high-speed bipolar transistors at high current densities

Gummel's integral charge-control relation (ICCR) IC= (const/Qp).exp (VBE/VT) is an important basis for developing self-consistent compact transistor models for the high-current region (including quasi-saturation). Such models are required for the simulation of future high-speed IC's with a high integration level. Unfortunately, the simplifying assumptions on which the ICCR is based seem to be doubtful especially for very fast transistors. Therefore, in this paper, the ICCR and its assumptions are checked via numerical simulation of such transistors (fT≈ 7-8 GHz). It is found that the one-dimensional ICCR is a fairly good approximation far into the high-current region. This satisfactory result is mainly due to the partial compensation of the influences of the spatially dependent doping concentration on both the electron mobility µnand the effective intrinsic density niewithin the product µnn²ie. Only in the emitter and in the emitter-base space-charge region there is a strong increase of this product which, in conjunction with the increasing contribution of the hole charge in these regions, was proved to be responsible for the errors observed at high current levels. The ICCR can also be applied to a two-dimensional transistor by additionally taking into account the excess hole charge stored outside the internal transistor for the determination of Qp. Thus the contribution of the minority charges can still be determined experimentally by measuring τf(IC).     

LED charge-control model and speed at high currents

A simple charge-control model for light-emitting diodes exists. The equation may be applied to both waveform analysis and synthesis (current preshaping). At high current levels, the cutoff frequencies are higher than predicted from the static high-injection lifetimes alone. The harmonic contents in the output may be frequency dependent at high current levels and cannot be completely determined from the static intensity-current curve.     

A new analytical model for the thermal resistance of deep-trench bipolar transistors

A new analytical model for the thermal resistance, temperature profile, and heat flow of deep-trench isolated (DTI) transistors is presented by taking the finite heat flow through the trenches into account. The new model is able to distinguish between the different contributions to the thermal resistance of the DTI structure and allows identification of the most dominant component. A detailed analysis of the substrate contribution shows that the substrate thermal resistance is overestimated in existing models. Results are compared with experimental data as well as numerical simulations and show a good agreement. The model can be used for process optimization and in a circuit simulator.     

A new electron-trapping model for the gate insulator of insulated gate field-effect transistors

In the present paper, a new model for electron trapping kinetics in the gate insulator of an insulated gate field-effect transistor (IGFET) is proposed. This model includes a continuous variation of the trapping cross section, σ_o, as a function of the number of filled traps,N _D . The dependency of σ_o is believed to be related physically to the annihilation, or buildup of coulombic charge, which effect has heretofore been neglected in first-order trapping kinetics that describe the entire defect concentration range. The result is that in order to model the experimental data fewer classes of trap cross sections are needed. AsN _D traps fill, the trapping cross section, σ_o, is assumed to be reduced by a factor (1 -N _D /N _T ) whereN _T is the total number of available traps per unit area. This decrease in δ_o is consistent, physically, with a concept of increasing repulsion of carriers as traps fill. This new model also indicates that the number of injected electrons needed to populate 99% of the total traps is about 20 times greater than that predicted by the existing first-order trapping kinetics model. Comparisons between the results of the new model and the first-order trapping kinetics model applied to experimental defect data are also given.     

A microwave model for high electron mobility transistors

In this paper, the authors present a high-frequency model for the high electron mobility transistor (HEMT). The model includes the distributed effects in the channel of the device through two newly developed wave equations in the linear and saturation regimes. The equations are solved taking into account the electric fields along and perpendicular to the flow of the current. The Y and S parameters are derived and the theoretical predictions of the model are compared with the experimental data and shown to be in good agreement over a wide range of frequencies     

A noise model for high electron mobility transistors

A model to explain the noise properties for AlGaAs/GaAs HEMT's, AlGaAs/InGaAs/GaAs pseudomorphic HEMT's (P-HEMT's) and GaAs/AlGaAs inverted HEMT's (I-HEMT's) is presented. The model Is based on a self-consistent solution of Schrodinger and Poisson's equations. The influence of the drain-source current, frequency and device parameters on the minimum noise figure F_min and minimum noise temperature T_min, for different HEMT structures are presented. The study shows that P-HEMT's have a better noise performance than the normal and inverted HEMT's. The present model predicts that a long gate P-HEMT device will exhibit a better noise performance than a conventional HEMT. There is a range of doped epilayer thickness where minimum noise figure is a minimum for pseudomorphic HEMT's which is not observed in conventional and inverted HEMT's. The calculated noise properties are compared with experimental data and the results show excellent agreement for all devices     

Breakdown-speed considerations in InP/InGaAs single- anddouble-heterostructure bipolar transistors

The breakdown and speed characteristics of InP/InGaAs single and double HBTs are presented. Temperature-dependent two- and three-terminal measurements suggest that avalanche impact ionization is the dominant breakdown mechanism in InGaAs collector HBTs. Monte Carlo techniques and 1D drift-diffusion modeling are used for speed and breakdown simulation, respectively. Special doping profiles are evaluated for improving the breakdown-speed characteristics of single HBTs (SHBTs) with conventional uniformly doped InGaAs collectors. Double HBTs (DHBTs) outperform all SHBTs in terms of speed-breakdown tradeoffs as long as they use graded base-collector junctions or they operate under sufficiently high collector-emitter voltage conditions. A cutoff frequency of 200 GHz was found to be feasible with graded DHBTs, and breakdown voltages up to 4.6 V were evaluated with a 3000-Å-thick collector. Nongraded DHBTs can be optimized to perform better in terms of speed-breakdown tradeoffs provided that a high collector doping is used     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

Determination of the physical parameters of transistors of single- and double-diffused structure

This paper is concerned with the estimation of physical parameters of the internal device structure of transistors in which the collector-base junction is of gradual (diffused) transition. The parameters evaluated are the dimensional quantities of base width, depletion layer width, and junction area, together with those that characterize the impurity density distribution in the base and other regions according to some representative functional expression. Previous determinations of such parameters have been restricted to devices of step (alloy) junction type, but here single- and double-diffused structures, in which the collector junction is graded, are considered. The estimation of physical parameters is carried out in terms of relatively simply measured properties of the transistor--in particular, the dependence of base transit time and junction capacitance on operating bias conditions. The theoretical basis of the determination is developed on the assumption of a simplified model of the device structure in which the major part of the base region and the collector are represented by an exponential distribution of impurity density, while a possible opposing field region near the emitter is considered to be of linear grading. In the analysis of this model, the position-dependence of the diffusion and mobility coefficients is taken into account. Experimental results show that consistent evaluation of the physical parameters of the device (viz, of its model representation) is possible for a range of structural types.