金属栅将取代多晶硅栅

为了克服器件尺寸缩小达到O．lum时,与多晶硅栅和薄栅氧化物有关的诸多问题,如栅耗尽、高阻栅、沟道区内的棚渗透、栅氧化隧道漏泄等等,也许很有必要采用金属栅和高k柳材料。1999年在旧金山召开的国际电子器件会议上,讨论了金属棚和可替换栅介质材料。如东芝公司微电子工程实验室具体介绍了开发生产金属栅的镶嵌工艺,以及工艺中所用到的高介质常数栅绝缘体（Ta刃。）。当浅沟槽隔离（ST）形成后,就进行源／漏注入,与用生长在虚拟棚氧化物上的SIP4／多晶硅薄膜制作的虚拟栅自对准。用LPCVD淀积预金属介质膜SIO。,并用CMP平面…     

MOS VLSI难熔栅述评

随着芯片尺寸和集成电路密度的不断增加,多晶硅互连线的电阻限制了总的电路性能。本文将对用于增强或代替多晶硅的难熔栅的现状进行评论。所讨论的栅结构有单层难熔金属栅及金属硅化物栅和含有硅化物的多晶硅-金属复合结构栅。探讨的一般问题包括:和现行MOS工艺的相容性,长期可靠性和按比例缩小到亚微米工艺的能力。涉及的具体问题有:难熔金属栅的钝化,和应力有关的难熔栅的粘附性,多晶硅化物的图形形成和自对准硅化物结构的选择形成。对用或未用难熔栅的具有当代工艺水平的256K动态RAM电路也作了评论。最后研究了难熔栅工艺的发展前途。     

下一代栅材料-难熔金属

随着晶体管尺寸的缩小,传统的多晶硅栅存在的多晶硅栅耗尽效应、过高的栅电阻和PMOS管的硼穿透效应成为晶体管尺寸进一步缩小的障碍.而难熔金属栅则被认为是最有希望的替代者.它可以很好的解决多晶硅栅面临的这些问题.本文主要介绍了选择难熔金属栅材料所需考虑的因素以及五种主要的制备工艺,并对比了它们各自的优缺点.     

CCD栅介质工艺对多晶硅层间介质的影响

CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响.采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响.研究结果表明:栅介质工艺对多晶硅层间介质形貌具有显著的影响.栅介质氮化硅淀积后进行氧化,随着氧化时间延长,靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大.增加氮化硅氧化时间到320 min,多晶硅层间薄弱区氧化层厚度增加到227 nm.在前一次多晶硅氧化后淀积一层15 nm厚氮化硅,能够很好地填充多晶硅层间介质空隙区,不会对CCD工作电压产生不利的影响.     

用镶嵌工艺制作金属/高k晶体管

东芝公司的研究人员认为,２ｍｍ以下的薄栅介质是开发高性能晶体管的最佳材料。这意味着栅材料从现在采用的重掺杂多晶硅栅和ＳｉＯ２栅氧化层向金属栅和高ｋ栅介质材料发展。 金属栅与多晶硅栅相比,其优点是不受栅耗尽效应的影响。高ｋ介质的优点是介质材料具有较高的介质常数（ｋ值）以及较低的隧道电流密度。同时,由于它们具有较大的电容,所以在相似的电特性下,能淀积的膜层厚度比二氧化硅膜厚。高ｋ材料包括Ｔａ氧化层、Ｔｉ氧化层、Ｚｒ氧化层以及Ｈｆ氧化层。 促使开发镶嵌栅工艺的一个因素是用反应离子刻蚀薄栅氧化层图形太难,…     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

一种无栅氧化物介电强度退化的二硅化钼/薄多晶硅栅新工艺

本文详细地分析了高温退火后在二硅化钼/薄n~+多晶硅(<1000A)栅结构中栅氧化层介电强度退化的情况。同时分析了栅氧化层绝缘特性和多晶硅中磷浓度、多晶硅原生氧化物,二硅化钼薄层电阻等各方面因素之间的关系,给出了二硅化钼、多晶硅、栅氧化物结构扫描电子显微镜、透射电子显微镜的观测结果。通过分析得出下列结论:高温退火时,在有阻挡层存在的情况下(阻挡层指二硅化钼淀积之前所形成的多硅上原生的厚氧化物),多晶硅与硅化钼局部作用会透过薄多晶硅层造成栅氧化物的损坏。根据分析结果,我们研究了一种没有介电强度退化的Mosi_2/薄Poly—si栅工艺。该工艺将二硅化钼直接淀积到未掺杂多晶硅上,从而控制多晶硅原生氧化物的生长,然后再将磷注入到二硅化钼中。这种工艺提供了很好的栅氧化层介电强度(薄到500A的多晶硅栅器件也是如此),易干法腐蚀,不产生多晶硅钻蚀,器件特性稳定,比通常的多晶硅栅工艺可靠性好。     

在多晶硅掺杂/活化处理过程中栅氧化层的性能退化

在MOS电路制作中,掺杂多晶硅膜的应用已经成为非常重要的半导体技术之一。但是,本文将描述多晶硅掺杂/活化处理过程中产生的缺陷可以严重地影响栅氧化物的性能。无论是否采用离子注入,多晶硅的原位掺杂剂淀积,或旋转源扩散到多晶硅等方法进行掺杂处理,采用150～400(?)的栅氧化物腐蚀的电容器,其成品率都随着掺杂剂浓度的增加,活化温度的升高以及活化时间的增长而愈来愈降低。在重掺杂多晶硅中,对于亚微米CMOS栅工艺,在栅氧化物内,经BF_2~ 或As自对准源/漏注入和活化后,其缺陷密度被证明是接近于10cm~(-2)。另一方面,在低剂量注入和活化后,如用于硅化物多栅工艺,缺陷密度仅仅为0.002cm~(-2)。这些结果对于兆位存贮元件的成品率可能有很大影响。     

用于CMOS工艺的双功函数Ni全硅化物金属栅

研究了Ni全硅化物金属栅功函数调整技术.研究表明,通过在多晶硅硅化前向多晶硅栅内注入杂质能够有效地调整Ni全硅化物金属栅的栅功函数.通过注入p型或n型杂质,如BF2,As或P,能够将Ni全硅化物金属栅的功函数调高或调低,以分别满足pMOS管和nMOS管的要求.但是注入大剂量的As杂质会导致分层现象和EOT变大,因此As不适合用来调节Ni全硅化物金属栅的栅功函数.由于FUSI工艺会导致全硅化金属栅电容EOT减小,全硅化金属栅电容的栅极泄漏电流大于多晶硅栅电容.     

高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

用于CMOS工艺的双功函数Ni全硅化物金属栅

研究了Ni全硅化物金属栅功函数调整技术.研究表明,通过在多晶硅硅化前向多晶硅栅内注入杂质能够有效地调整Ni全硅化物金属栅的栅功函数.通过注入p型或n型杂质,如BF2,As或P,能够将Ni全硅化物金属栅的功函数调高或调低,以分别满足pMOS管和nMOS管的要求.但是注入大剂量的As杂质会导致分层现象和EOT变大,因此As不适合用来调节Ni全硅化物金属栅的栅功函数.由于FUSI工艺会导致全硅化金属栅电容EOT减小,全硅化金属栅电容的栅极泄漏电流大于多晶硅栅电容.     

高k栅介质的可靠性问题

随着集成电路特征尺寸的不断缩短,利用先进的高k/金属栅堆叠来取代传统的SiO2/多晶硅栅结构成为微电子技术发展的必然,确保这些新的栅极堆叠类型具有足够的可靠性是非常重要的.综述了高k栅介质可靠性的研究现状,阐明了瞬态充电效应导致的阈值电压不可靠问题,对偏压温度不稳定现象(BTI)和高k击穿特性进行了探讨.     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers

Dual-work-function metal gates fabricated by full silicidation (FUSI) of Co-Ni bi-layer with doped poly-Si were investigated for the first time, along with single-metal FUSI systems of CoSi/sub 2/ and NiSi. Complete conversion of poly-Si into Co-Ni alloy silicided metal gate (FUSI) Co/sub x/Ni/sub 1-x/Si/sub 2/ was demonstrated. Although a linear relationship between work function and Ni percentage was observed for FUSI of undoped poly-Si systems, the work functions of doped Co/sub x/Ni/sub 1-x/Si/sub 2/ are almost identical to those of doped NiSi FUSI metal gates. The alloy FUSI metal gates explored in this letter provide a new class of metal gates for CMOS devices that combine the advantages of both NiSi and CoSi/sub 2/, i.e., proper work function tunability of NiSi and high thermal stability of CoSi/sub 2/.     

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:Ni2Si, and Ni31Si12) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁ Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS     

Impact of Gate Electrodes on $hbox{1}/f$ Noise of Gate-All-Around Silicon Nanowire Transistors

The low-frequency (1/f) noise of gate-all-around silicon nanowire transistors (SNWTs) with different gate electrodes (poly-Si gate, doped fully silicided (FUSI) gate, and undoped FUSI gate) is studied in the strong-inversion linear region. It shows that the gate electrodes have a strong impact on the 1/f noise of the SNWTs. The highest noise is observed in the SNWTs with a poly-Si gate, compared to their FUSI-gate counterparts. The observations are explained according to the number fluctuation with correlated mobility fluctuation theory by assuming that the correlated mobility scattering is better screened in the case of an undoped FUSI gate. However, the doped FUSI gate with silicidation-induced impurity segregation at the gate/SiO₂ interface gives rise to extra mobility scattering.     

Dual work function metal gates using full nickel silicidation of doped poly-Si

This paper investigates the work function adjustment on fully silicided (FUSI) NiSi metal gates for dual-gate CMOS, and how it is effected by the poly-Si dopants. By comparing FUSI on As-, B-, and undoped poly-Si using the same p-Si substrates, it is shown that both As and B influence the work function of NiSi FUSI gate significantly, with As showing more effects than B possibly due to more As pile-up at the NiSi-SiO/sub 2/ interface. No degradations on the underlying gate dielectrics are observed in terms of interface state density (D/sub it/), fixed oxide charges, leakage current, and breakdown voltage, suggesting that NiSi FUSI is compatible with dual-gate CMOS processing.     

A Millisecond-Anneal-Assisted Selective Fully Silicided (FUSI) Gate Process

We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (MSA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform $hbox{P}^{+}$ FUSI gates for PMOSFETs while preserving a FUSI-free $hbox{N}^{+}$ poly-Si gate for NMOSFETs with the feature size down to 30 nm. A 20% improvement in FUSI-gated PMOSFET $I_{rm on}$ –$I_{rm off}$ is measured, which can be attributed to the enhanced hole mobility and the elimination of $hbox{P}^{+}$ poly-gate depletion.      

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.