Experimental study on current gain of BSIT

A means to improve the current gain hFSof the BSIT in a high drain current region has been derived from an experimental study about the dependency of the hFSversus drain current relationship on the channel width, the gate junction depth, and the impurity concentration in the n^-high-resistivity drain region. The BSIT, designed in this manner and including 9000 channels in a chip of 7 × 10 mm², exhibits a current gain over 100 and high switching speeds, a rise time of 200 ns, a storage time of 200 ns and a fall time of 25 ns at a drain current of 50 A.     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

Effect of hydrogen-argon mixing for sputtered aluminum metallization on MOS devices

Effects of aluminum films deposited by RF diode sputtering in hydrogen and argon mixed gases have been investigated in n-channel silicon-gate MOS transistors and capacitors. Positive fixed oxide charge Qoxand acceptor-type surface states Nsscreated by the sputter metallization process have been confirmed experimentally. The threshold voltage Vthof a transistor metallized with aluminum sputtered in pure argon was found to be shifted toward positive voltages and its transconductance was markedly lowered due to acceptor-type surface states. Hydrogen mixing in the sputtering argon gas minimizes Qoxand Nss, resulting in small Vthand gmchanges.     

Comments on "Measurements and interpretation of low frequency noise in FET's"

It is shown that, according to the theories of 1/f noise in MOST's by Klaassen [1] and Berz [2], the mean-square equivalent noise voltage at the gate Vgn²is proportional to the effective surface state density Nss, and not to NssVg(Vg= gate voltage), as was stated for these theories by Das and Moore. Therefore, contrary to what was concluded by Das and Moore, there is no conflict between these theories and the experimental results by Das and Moore which show that Vgn²varies with gate voltage as Nss.     

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the ID-VDcharacteristics could be simulated by computer model based on the physical effects.     

Breakdowns in Si JFET's

A two-dimensional numerical analysis to clarify the breakdown phenomena in Si n-type JFET is described. In this analysis, the continuity equation for minority carriers is introduced to consider the effect of avalanche multiplication. The heat conduction equation is also taken into account to include the thermal effect on the breakdown voltage. The results obtained are: 1) the mechanisms of excess gate current (EGC), current-mode second breakdown (CSB), and thermal-mode second breakdown (TSB). 2) The effects of how channel impurity concentration Nc, drain current ID, and applied drain voltage VDGaffect EGC, CSB, and TSB are also reported.     

An improved method of MOSFET modeling and parameter extraction

A method is presented to accurately determine MOSFET modeling parameters from a single linear region (VDS< 2kBT/q)ID- VGSmeasurement based on the operation of a single transistor in the strongly inverted regime. The intrinsic values of the surface scattering parameter θsand the transistor gain β0may be separated from the series resistance Rsand drain bias VDSeffects while including band bending beyond the 2φFpoint. The mobility (excluding surface scattering effects), threshold voltage, bulk doping, and flat-band voltage are also determined.     

Characterization of deep levels in modulation-doped AlGaAs/GaAs FET's

Deep levels in modulation-doped field-effect transistors (MODFET's) fabricated from MBE-grown AlGaAs/GaAs heterostructures, have been characterized by a modified deep-level transient spectroscopy (DLTS) technique. Assuming donor-like traps in the AlGaAs layer, it is shown that the threshold voltage Vtvaries exponentially with time under pulsed-biased conditions. This result is verified experimentally by observing the transient in the drain current IDin long-gate FET's biased in saturation. The resulting Δ √{I_{D}} DLTS spectrum reveals an electron trap with an activation energy of 0.472 eV in Si-doped Al0.3Ga0.7As.     

Analysis of electron trapping location in gated and ungated inverted-structure HEMT's

Using gated (10-µm gate length) and ungated Inverted-Structure HEMT's (GaAs/n-AlGaAs) with three microprobes, potential profiles along the channel were measured as a function of drain voltage VD. The gated FET was found to show the persistent enhancement of the channel resistance near drain region at VDof more than 1.5 V, on the other hand, the ungated FET showed it near source region at VDof more than 0.8 V, in the dark at 77 K. These effects are caused by the electron trapping in n-AlGaAs layers, and the intensity of electron trapping in the ungated FET was found to be stronger than that in the gated FET.     

Drain conductance of junction gate FET's in the hot electron range

A new model is proposed for the drain conductance of J-FET's in the hot electron range. The model is based on a physical picture revealed through two-dimensional numerical analysis. The two-dimensional analysis shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory. Because of this gradual change, electrons can remain after the pinch-off and contribute to the drain current. Although the high electric field causes the electron velocity to saturate, the drift velocity vector rotates into the x axis (source-to-drain) with the increase in the drain voltage. The increase in the x component Vxof the drift velocity gives rise to a small increase in drain current, that is, a finite drain conductance. The proposed model takes into account the above two essential features, gradual change in electron distribution, and the rotation of the velocity vector. This model is constructed in a single formulation which describes the current-voltage characteristics from the linear to the saturated drain-current region. Theoretical calculations agree quite well with the experiment on GaAs Schottky barrier gate FET's.     

非晶IGZO薄膜晶体管开启区电流的解析模型

对非晶In-Ga-Zn-Oxide薄膜晶体管,假设能隙中陷阱态密度呈指数分布,给出了解析的电流模型。运用薄层电荷近似的方法推导陷落电荷和自由电荷表达式,并基于此给出了基于表面势的电流表达式。在此电流表达式的基础上,通过泰勒展开,给出了基于阈值电压的电流表达式。基于表面势和基于阈值电压的电流表达式的计算结果与测量数据相比较,符合得很好。     

AlGaN/GaN高电子迁移率晶体管大信号I-V特性模型

对非线性电流源Ids(Vgs,Vds)的准确描述是Al GaN/GaN HEMT大信号模型的最重要部分之一.Materka模型考虑了夹断电压与Vds的关系,其模型参数只有三个,但是Ids与Vgs的平方关系不符合实际,计算结果与测量数据有误差.我们在考虑了栅电压与漏电流的关系及不同栅压区漏电流随漏电压斜率改变的基础上,提出了改进的高电子迁移率晶体管(HEMT)的直流特性模型.采用这个模型,计算了Al GaN/GaN HEMT器件的大信号I-V特性,并与实际测量数据进行了比较.实验结果表明改进的模型更精确,Ids与Vgs的呈2.5次方的指数关系.     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.     

Modeling of the subthreshold characteristics of SOI MOSFETs withfloating body

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current     

Analytical drain current model for amorphous IGZO thin-film transistors in above-threshold regime

An analytical drain current model is presented for amorphous In-Ga-Zn-oxide thin-film transistors in the above-threshold regime,assuming an exponential trap states density within the bandgap.Using a charge sheet approximation,the trapped and free charge expressions are calculated,then the surface potential based drain current expression is developed.Moreover,threshold voltage based drain current expressions are presented using the Taylor expansion to the surface potential based drain current expression.The calculated results of the surface potential based and threshold voltage based drain current expressions are compared with experimental data and good agreements are achieved.     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

Electrical damage in MOS devices by RF diode sputtered aluminum metallization

Electrical damage induced by RF diode sputtered aluminum metallization has been investigated in n-channel silicon gate MOS transistors and capacitors. The following results were obtained: 1) Positive fixed oxide charge Qoxand surface state Nssare created near Si-SiO2interface. 2) A majority of Nssact as acceptor-type surface state. Then, threshold voltages of transistors shift toward positive voltage, due to the acceptor,type surface state, in spite of creation of Qox. 3) Dependences of threshold voltage on substrate voltage in the as-deposited sample become greater due to the metallization. 4) Electrical damage for both devices Can be effectively reduced by annealing them in forming gas at 450°C for 20 min.     

A theoretical model for the current-voltage characteristics of afloating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell     

Radiation damage of thermally oxidized MOS capacitors

The influence of preparation parameters and the effect of X-rays (150 keV, 10⁴rad (Si)) on oxide charge Qoxand interface state density Nssin thermally oxidized MOS varactors under different biasing conditions during irradiation has been investigated. The interface state density was determined by the ac conductance method before and after irradiation. The oxide charge has been evaluated with regard to the charge Qssof the interface states. Qsshas beeu discussed with the aid of simple models concerning the energetic distribution and recharge character of the interface states. The results indicate a similar dependence between flatband voltage, interface state density, and normalized oxide charge density as a function of gate bias during irradiation. Furthermore, the so-called "oxidation triangle" of oxide charge before irradiation exists for interface states as well. Calculations on the basis of the Schottky barrier model of the irradiated MOS structure show that the radiation-induced charge exists at both interfaces in the oxide layer. Radiation tolerance of the MOS capacitors as a function of technological parameters is discussed.     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.