N-Channel MOSFETs with WSi2gate

Tungsten silicide gate depletion- and enhancement-mode NMOS transistors were fabricated. The transistor characteristics revealed the excellent compatability of WSi2as gate electrode for MOS integrated circuits. Electron mobility of channel at saturation were found to be 210 cm²/v sec for enhancement-mode transistor and 110 cm²/v sec for depletion-mode transistor.     

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO2) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO2laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm²/V sec and leakage currents < 10 pA, for a Channel length of 12 µm and width of 20 µm. Achievement of high-performance TFT's with the combined features of microcrack suppression, preferred orientation, and selected-area crystallization render CO2- laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.     

Device quality MOS Gate insulators: Sputter deposition and low temperature processing

A series of n-channel, Al-gate MOS transistors were fabricated using reactively sputtered SiO2as the gate insulator. The SiO2was deposited at low temperatures and low RF powers, and during subsequent processing was not subjected to temperatures in excess of 465°C. Test results showed that for gate oxides deposited at 20 W, the measured breakdown strength was 3-4 MV/cm with interface trapped charge density of 4-8 × 10¹⁰cm^-2and that the resulting electron mobility of the transistor was 470 cm²/V.s. After annealing in nitrogen at 1000°C, the deposited oxides exhibited electrical properties which are very similar to those of thermally grown SiO2.     

XeCl Excimer laser annealing used in the fabrication of poly-Si TFT's

Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm²/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm². This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.     

Device characterization on monocrystalline silicon grown over SiO2by the ELO (epitaxial lateral overgrowth) process

MOS and lateral bipolar transistors have been fabricated on epitaxial silicon layers which have been laterally overgrown over SiO2. These device characteristics were than compared to those measured on devices fabricated on homoepitaxial silicon and bulk silicon. The measurements indicate essentially identical MOS device characteristics for all three materials with a typical hole field effect mobility of about 180 cm²/vs. Lifetime measurements using pulsed C-V techniques showed essentially the same values for ELO material and homoepitaxial material with the ELO value being about 20 µS for 10¹⁵cm^-3doping level. These lifetime values correlate will with diode and bipolar transistor measurements.     

Fabrication of Si MOSFET's using neutron-irradiated Silicon as semi-insulating substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The mobility of carrier in the channel is about 100 cm²/V . s for p-channel MOSFET's and 300 cm²/V . s for n-channel devices. This structure has inherent advantages such as crystallographically single crystalline.     

Laser annealing effects on the electrical characteristics of SOS transistors

Successful incorporation of laser annealing techniques into standard processing methods requires that the electrical characteristics of the devices not be degraded. In this work, a range of energy densities from pulsed u.v. and visible lasers which can be utilized in silicon on sapphire (SOS) technology to improve device performance without introducing any deleterious side effects is determined experimentally. Silicon islands were photolithographically defined and chemically etched (KOH) on standard SOS wafers which were subsequently exposed to pulsed (25 nsec) ruby ($\text{λ = 6943}\text{A}\text{?}$) and excimer ($\text{λ = 2490}\text{A}\text{?}$) laser radiation. Comparative studies of the effect of front and back side (through the sapphire) irradiation of the silicon on device performance were conducted. Using standard processing techniques, MOS transistors were fabricated after laser irradiation and electrically characterized. It was found that under certain conditions utilization of lasers in SOS processing, can result in an increase in the interface state density at both the top 〈100〉 Si-SiO₂ interface and the bottom Al₂O₃-Si interface. However, a set of conditions exists, in which it is possible to apply laser annealing to standard SOS processing so as to increase MOS/SOS transistor channel mobility by over 30% without causing any degradation of the device electrical characteristics.     

Fabrication of SOS MOSFETs using two-step doping with excimer laser

Using two-step doping with excimer laser, p-channel MOSFETs were fabricated in thin silicon films on sapphire (SOS). Source and drain p ⁺ layers were formed using two-step doping with only one melting pulse of excimer laser. Devices were processed at room temperature except for the LPCVD gate oxide deposition at 450°C. High-quality thin film transistors (TFTs) were fabricated with on/off current ratio of 7 and a field effect hole mobility of 145 cm²/V s     

Device fabrication in {100} silicon-on-oxide produced by a scanning CW-laser-induced lateral seeding technique

By using a CW-laser-beam-induced lateral seeding technique, which is a zone-melting crystal-growth process, single-crystal silicon-on-oxide with{100}orientation has been obtained. To adopt this process for silicon-on-insulator (SOI) MOS transistor fabrication, a masking level has been added to an exisiting n-MOSFET mask set so that a fully recessed oxide layer may be grown in selected regions of a silicon wafer; the exposed silicon region becomes the seed region. After depositing a 0.5-µm-thick layer of undoped low-pressure CVD polysilicon on the wafer, a laser process is performed to induce epitaxial growth in the polysilicon-on-silicon region, which in turn seeds the zone growth of the polysilicon-on-oxide region as the beam is traversed across the surface of the wafer. N-channel MOS transistors have been fabricated in the silicon-on-oxide material using projection printing lithography. Both complete-island-etch (CIE) and LOCOS techniques have been used for device-to-device and device-to-substrate isolation. Surface electron mobilities as high as 740 cm²/V . s, comparable to that obtainable in bulk-type devices, have been measured in 5-µm channel-length devices. It is shown that the back interface between the recrystallized silicon and the oxide layer is the dominant contributor to the subthreshold leakage current due to a combined effect of a high fixed oxide charge density and drain-induced barrier lowering. A high dose (sim 10^{12}cm^-2) deep boron implantation centered at the back interface and a back-gate bias have been shown to be effective in suppressing the leakage current to as low as 1-pA/µm channel width at VDS= 2 V, comparable to the best results obtained in silicon-on-sapphire (SOS).     

j-MOS: A versatile power field-effect transistor

A novel field-effect transistor (FET) structure that is attractive for power control applications is proposed and demonstrated. It combines MOSFET structural features and junction FET function in a simple, self-aligned structure that we refer to as j-MOS. Lateral j-MOS transistors were fabricated in silicon-on-sapphire (SOS) with on-resistance as low as 2.5 Ω in 1 cm of channel width. From this result, we project that a vertical version of j-MOS can be fabricated in silicon-on-buried insulator (SOI) with a specific on-resistance ≤ 1 m Ω.cm², approximately a factor of two improvement over current power FET technology.     

Threshold voltage variations with temperature in MOS transistors

Variations with temperature in the threshold voltage of n- and p-channel MOS transistors are obtained by calculation as well as measurement, with the results comparing quite closely. The amount of voltage change per °C under normal operating conditions is found to be dependent upon the channel doping concentration. The calculations show that for either n- or p-channel devices the voltage change per °C is -4 mV/°C for an impurity concentration of 3 × 10¹⁶/cm³and -2 mV/°C for an impurity concentration of 10¹⁵/cm³. This information is important because if the MOS transistor is subjected to a changing temperature environment, the accompanying threshold voltage change may be intolerable.     

Transistors made in single-crystal SOI films

Test transistors with gate lengths ranging from 10 to 4 µm were made in laser-recrystallized silicon on insulator films. A capping layer of patterned antireflecting stripes of Si3N4was used to grow large single-crystals of silicon. MOS transistors show good electrical characteristics and a surface mobility up to 650 cm²/V.s for electrons. With the exception of the recrystallization procedure, the wafers followed a fully standard NMOS process, including the growth of a LOCOS field oxide.     

MOSFET Characteristics in low-temperature plasma-enhanced chemical vapor deposited epitaxial silicon

The fabrication of high-quality MOSFET's using low-temperature (750-800°C) Plasma-Enhanced Chemical Vapor Deposited (PECVD) epitaxial silicon is reported here for the first time. The fabricated devices include PMOS transistors with hole channel mobilities of 213 cm²/V.s (versus 218 cm²/V.s in bulk silicon controls) and NMOS transistors with electron channel mobilities of 520 cm²/V.s (versus 560 cm²/V.s in bulk silicon controls), and with an on-current to off-current ratio of 10⁷. These results indicate that epitaxial silicon films deposited by the PECVD technique are of high quality, even though the epitaxial deposition temperature was only 750-800°C.     

Dependence of electron channel mobility on Si-SiO2interface microroughness

The effect of the Si-SiO₂ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH₄ OH in the NH₄OH-H₂O₂-H₂O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO₂ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm²/V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5×10¹⁷ cm^-3, i.e. the electron bulk mobility is 400 cm²/V-s. It goes down to 100 cm²/V-s when the interface microroughness exceeds 1 nm     

p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.     

High-Performance Self-Aligned Bottom-Gate Low-Temperature Poly-Silicon Thin-Film Transistors With Excimer Laser Crystallization

In this letter, high-performance bottom-gate (BG) low-temperature poly-silicon thin-film transistors (TFT) with excimer laser crystallization have been demonstrated using self-aligned (SA) backside photolithography exposure. The grains with lateral grain size of about 0.75 mum could be artificially grown in the channel region via the super-lateral-growth phenomenon fabricated by excimer laser irradiation. Consequently, SA-BG TFT with the channel length of 1 mum exhibited field-effect mobility reaching 193 cm²/V ldr s without hydrogenation, while the mobility of the conventional non-SA-BG TFT and conventional SA top-gate one were about 17.8 and 103 cm²/V ldr s, respectively. Moreover, SA-BG TFT showed higher device uniformity and wider process window owing to the homogenous lateral grains crystallized from the channel steps near the BG edges.     

101-Stage 2 µm gate ring oscillators in laser-grown silicon islands embedded in SiO2

E/D MOS test transistors and 101-stage 2 µm gate E/D MOS ring oscillators were fabricated in laser-grown single- and multicrystal islands embedded in oxide substrates. Most transistors showed goodI-Vcharacteristics, short-channel effects, and kink effects. Ring oscillators had a switching delay per stage (τPd) of 0.4 ns and a power-delay product (τ_{Pd} middot P_{d}) of 2.5 PJ at a supply voltage (VDD) of 10-15 V. It was noted that different crystal orientations of the islands posed no difficulty in processing and VTcontrol when applied to short channel devices, and that enhanced boundary diffusion results in occasional malfunctional transistors and erroneous high surface electron mobilities (µse).     

Integrated amorphous and polycrystalline silicon thin-filmtransistors in a single silicon layer

Using a masked hydrogen plasma treatment to spatially control the crystallization of amorphous silicon to polycrystalline silicon in desired areas, amorphous and polycrystalline silicon thin-film transistors (TFTs) with good performance have been integrated in a single film of silicon without laser processing. Both transistors are top gate and shared all process steps. The polycrystalline silicon transistors have an electron mobility in the linear regime of ~15 cm²/Vs, the amorphous silicon transistors have a linear mobility of ~0.7 cm²/Vs and both have an ON/OFF current ratios of >10⁵. Rehydrogenation of amorphous silicon after the 600°C crystallization anneal using another hydrogen plasma is the critical process step for the amorphous silicon transistor performance. The rehydrogenation power, time, and reactor history are the crucial details that are discussed in this paper     

Dual-Gate Graphene FETs With $f_{T}$ of 50 GHz

A dual-gate graphene field-effect transistor is presented, which shows improved radio-frequency (RF) performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm²/V · s, a cutoff frequency of 50 GHz is demonstrated in a 350-nm-gate-length device. This f_T value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOS field-effect transistors at the same gate length, illustrating the potential of graphene for RF applications.     

Characteristics of inversion-channel and buried-channel MOS devicesin 6H-SiC

Inversion-channel and buried-channel gate-controlled diodes and MOSFET's are investigated in the wide bandgap semiconductor 6H-SiC. These devices are fabricated using thermal oxidation and ion implantation. The gate-controlled diodes allow room temperature measurement of surface states, which is difficult with MOS capacitors due to the 3 eV bandgap of 6H-SiC. An effective electron mobility of 20 cm²/Vs is measured for the inversion-channel devices and a bulk electron mobility of 180 cm²/Vs is found in the channel of the buried-channel MOSFET. The buried-channel transistor is the first ion-implanted channel device in SIC and the first buried-channel MOSFET in the 6H-SiC polytype