A Built-in-Self-Test Σ-Δ ADC Prototype

This paper presents a built-in-self-test (BIST) Σ-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard ??6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.     

A design of order-adjustable Σ∆ modulator for high performance micro-machined accelerometers

Sigma-delta modulation has been widely used in micro-machined accelerometers. Previous researches are mainly focused on increasing the order of the sigma-delta modulator for the mechanical sensor to improving the performance of the micro-machined accelerometers. These designs performed well in high resolution acceleration measurement, but they are insufficient in balancing the proof mass quickly while the micro-machined accelerometer is working. In this paper, the design of order-adjustable micro-machined accelerometer is proposed. It employs a mechanical sensor to balance the proof mass, and a fifth order MEMS accelerator to measure the acceleration with high resolution. Furthermore, this work shows an optimized design with a SQNR of 156.5 and 73.6 dB which can accurately measure the acceleration input and quickly balance the proof mass, respectively.     

An 18-bit high performance audio Σ-△ D/A converter

A multi-bit quantized high performance sigma-delta (Σ-△) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simpler Σ-△ modulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average (DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm2.The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB,respectively.     

A Class-C VCO Based Σ-Δ Fraction-N Frequency Synthesizer with AFC for 802.11ah Applications

A 1.4-2 GHz phase-locked loop (PLL) Σ-Δ fraction-N frequency synthesizer with automatic frequency control (AFC) for 802.11ah applications is presented. A class-C voltage control oscillator (VCO) ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order Σ-Δ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of < -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.     

A Novel Statistical Technique for the Estimation of DC Stability in Higher-Order Σ-Δ A/D Converters

The existing techniques available for the statistical estimation of the dc input signal stability in general-order Σ-Δ analog-to-digital (A/D) converters are based on the assumption that the constituent quantizer input signal has a Gaussian distribution. However, empirical investigations reveal that this assumption holds adequately true only for the special case of conventional first-order Σ-Δ A/D converters. This paper presents an alternative technique for the accurate estimation of the dc input signal stability for higher-order Σ-Δ A/D converters. This estimation technique is based on the practical assumption that the constituent quantizer operates in its overload-free region, permitting the characterization of the quantizer output signal digit-pattern for the determination of the statistical moments of the corresponding quantizer input signal. The resulting statistical moments are subsequently incorporated in a Gram-Charlier series for an accurate quasi-linear modeling of the quantizer. A typical application example is given to demonstrate the accuracy of the proposed statistical technique for predicting the existence of multiple regions of instability and stability in the Σ-Δ A/D converter operation, and particularly for predicting the point where the A/D converter operation becomes unstable.     

基于MASH结构的24 bit Σ-Δ A/D转换器

设计了一种离散时间型24位Σ-Δ A/D转换器。该A/D转换器基于级联噪声整形(MASH)结构设计,整个转换器由前置可编程增益放大器、级联调制器和数字抽取滤波器等模块组成。该A/D转换器采用标准0.18 μm CMOS工艺实现,版图总面积为6 mm²。测试结果表明,在16 kS/s输出数据速率下,该A/D转换器的信噪比为106 dB,无杂散动态范围为110 dB,功耗仅为20 mW。     

A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Σ-Δ Modulators

Evaluating the digital stimuli used in the design-for-digital-testability (DfDT) Σ-Δ modulator is a time-consuming task due to its oversampling and non-linear nature. Although behavioral simulations can substantially improve the simulation speed, conventional behavioral models fail to provide accurate enough signal-to-noise ratio (SNR) predictions for this particular application. In this paper, a fully-settled linear behavior plus noise (FSLB+N) model for the DfDT Σ-Δ modulator is presented to improve both the accuracy and the speed of the behavioral simulations. The model includes the following parameters: the finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), as well as the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With the proposed model, the behavioral simulation results demonstrate a high correlation with the measurement data. On average, the SNR difference between the simulation and the measurement is –1.1 dB with a maximum of 0.05 dB and a minimum of –2.2 dB. Comparing with the circuit-level simulation using HSPICE, the behavioral simulation with the FSLB+N model is 1,190,000 times faster. The proposed model not only can be used for evaluating the digital stimulus candidates, but also can be applied to system-level simulations of the mixed-signal design with an embedded DfDT Σ-Δ modulator.

一种0.35 μm CMOS高精度Σ-Δ A/D转换器

提出了一种应用于MEMS压力传感器的高精度Σ-Δ A/D转换器。该电路由Σ-Δ调制器和数字抽取滤波器组成。其中,Σ-Δ调制器采用3阶前馈、单环、单比特量化结构。数字抽取滤波器由级联积分梳状(CIC)滤波器、补偿滤波器和半带滤波器(HBF)组成。采用TSMC 0.35 μm CMOS工艺和Matlab模型对电路进行设计与后仿验证。结果表明,该Σ-Δ A/D转换器的过采样比为2 048,信噪比为112.3 dB,精度为18.36 位,带宽为200 Hz,输入采样频率为819.2 kHz,通带波纹系数为±0.01 dB,阻带增益衰减为120 dB,输出动态范围为110.6 dB。     

0.18μm CMOS Σ-Δ ADC用数字抽取滤波器设计

采用标准0.18μm CMOS工艺,设计了一种应用于UHF RFIDΣ-Δ模数转换器的数字抽取滤波器,并完成其前后仿真、逻辑综合、布局布线及版图实现等全流程.该滤波器主要实现滤波和降采样功能,由梳状滤波器、补偿滤波器和半带滤波器级联组成.合理选择各级滤波器的结构、阶数并采用规范符号编码(CSD)对其系数进行优化.仿真结果表明:采样频率为64MHz,过采样率为32的二阶Σ-Δ调制器的输出1位码流经过该滤波器滤波后,信噪比达到53.8dB;在1.8V工作电压下,功耗约为15mW.版图尺寸0.45mm×0.45mm,能够满足RFID中模数转换器的要求.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

An 18-bit high performance audio ∑-△D/A converter

A multi-bit quantized high performance sigma-delta(Σ-Δ) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average(DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between ...     

A 470 μA direct readout circuit for electret and MEMS digital microphones

A direct readout circuit configurable for electret or MEMS digital microphones is presented. The circuit includes a transducer buffer, a programmable preamplifier, a ΣΔ modulator, a bandgap reference, a clock detection circuit, and a stability recovery system. The prototype achieves a signal-to-noise-and distortion of 63 dB A-weighted at 1 Pa sound level with a consumption of 470 μA at 1.8 V supply voltage. The active area is 0.72 mm² in a 0.25 μm CMOS process with MIM capacitor option.     

低功耗音频Δ -∑ D／A转换器

设计了一种适用于音频应用的16位D/A转换器.芯片集成了内插滤波器、Δ-Σ调制器和D类功放,可以独立完成带宽为8 kHz的音频数字信号到模拟信号的转换.内插滤波器完成64倍过采样并消除镜像信号,Δ-Σ调制器实现16位的转换精度.在驱动8 Ω负载时,D类功放实现97 dB的动态范围,最大输出功率达到100 mW,三次谐波小于-100 dB;同时,功率效率大于90%,特别适合低功耗应用领域.设计采用标准0.18 μm CMOS工艺,芯片面积约为2 μm×2 μm.     

Fast patterning and dry-etch of SiNχ for high resolution nanoimprint templates

We developed a simplified nanofabrication process for imprint templates by fast speed electron beam lithography (EBL) and a dry etch technique on a SiNx substrate, intended for large area manufacturing. To this end,the highly sensitive chemically amplified resist (CAR), NEB-22, with negative tone was used. The EBL process first defines the template pattern in NEB-22, which is then directly used as an etching mask in the subsequent reactive ion etching (RIE) on the SiNx to form the desired templates. The properties of both e-beam lithography and dry etch of NEB-22 were carefully studied, indicating significant advantages of this process with some drawbacks compared to when Cr was used as an etching mask. Nevertheless, our results open up a good opportunity to fabricate high resolution imprint templates with the prospect of wafer scale manufacturing.     

A 2.1 μA wake-up circuit for Chinese ETC system

This paper proposes a low power wake-up baseband circuit used in Chinese Electronic Toll Collection (ETC) system. To reduce the static power consumption, a low power biasing strategy is proposed. The proposed circuit is fabricated in TSMC 0.18 μm technology with an area of 0.09 mm 2 . Its current consumption is only 2.1 μA under 1.8 V power supply. It achieves a sensitivity of 0.95 mV at room temperature with a variation of only ±28% over -35℃ to 105℃.     

A 65-nm low-noise low-cost ∑Δ modulator for audio applications

This paper introduces a low-noise low-cost ΣΔ modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier, not only is the flicker noise greatly inhibited, but also the power consumption is reduced. Also the area cost is relatively small. The modulator was implemented in a SMIC standard 65-nm CMOS process. Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio (SNDR) and 105 dB dynamic range (DR) over the 22.05-kHz audio band and occupies 0.16 mm². The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply, which is suitable for high-performance, low-cost audio codec applications.     

A 7.9 μA multi-step phase-domain ADC for GFSK demodulators

The phase-domain analog-to-digital converter (Ph-ADC) is proved to be more power efficient than traditional amplitude ADCs in wireless receivers . A low power multi-step Ph-ADC for zero intermediate frequency (IF) GFSK receivers as defined in Bluetooth low energy protocol is proposed in this paper. With dedicatedly designed binary code scheme and multi-step operation, the Ph-ADC requires only 52 current elements and one comparator, in contrast to the design in literature using 260 current elements and 8 comparators. Non-idealities due to transconductance errors and offset errors are theoretically analyzed, followed by a design strategy to minimize trip point errors. Simulation results show that the digital intensive Ph-ADC consumes only 7.9 μA current from a 1.8 V supply when implemented in a 180 nm CMOS process. Monte-Carlo simulations show that the maximum trip point error is only 2.3°, which is less than 1/8 least significant bit. When the Ph-ADC is used in a GFSK demodulator, the required IF E_b/N₀ is 13.5 dB to achieve a bit error rates of 0.1%.     

A high-performance,low-power ∑Δ ADC for digital audio applications

A high-performance low-power ∑Δ analog-to-digital converter (ADC) for digital audio applications is described.It consists of a 2-1 cascaded ∑Δ modulator and a decimation filter.Various design optimizations are implemented in the system design,circuit implementation and layout design,including a high-overload-level coefficientoptimized modulator architecture,a power-efficient class A/AB operational transconductance amplifier,as well as a multi-stage decimation filter conserving area and power consumption.The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process.The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2,which dissipates only 2.1 mA quiescent current in the analog circuits.