A novel structure of tightly coupled lines for MMIC/MHMIC couplersand phase shifters

In this paper, a new structure of tightly coupled lines compatible with monolithic-microwave integrated-circuit/miniature hybrid-microwave integrated-circuit (MMIC/MHMIC) technology is introduced. Different from previous designs, short subsections of two or more different coupled lines are alternatively connected together to achieve the needed performance of a single-section coupler or phase shifter. Theoretical calculations are given and some typical design data are provided. A design example of a wide-band coplanar-waveguide (CPW) quadrature coupler using standard MMIC foundry technology is provided. Only metal-insulator-metal (MIM) capacitors and air-bridges are used to achieve tight coupling-no via holes are necessary. Experimental results are in good agreement with simulations. The proposed structure of coupled lines is very flexible and easily achieves very tight coupling factors     

A low-impedance coplanar waveguide using an SrTiO3 thinfilm for GaAs power MMIC's

A novel structure for coplanar-waveguide transmission lines with low impedance and low loss is demonstrated in this paper. The new structure simply has a high dielectric SrTiO₃ thin film underneath the coplanar conductors. Due to the high dielectric constant of SrTiO₃, the coplanar line exhibited characteristic impedance as low as 18 Ω with a slot width of 5 μm and the center conductor width of 50 μm, while a conventional coplanar line on GaAs showed only 30 Ω with the same configuration. The newly developed coplanar structure is easily applicable for present GaAs monolithic-microwave integrated-circuit (MMIC) technology, especially for power MMIC's and low-impedance devices     

Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

In this paper, we provide an extensive experimental and theoretical study of the benefits of patterned ground shield interconnect transmission lines over more conventional layouts in advanced integrated-circuit processes. As part of this experimental work, we present the first comparative study taken on truly differential transmission line test structures. Our experimental results obtained on transmission lines with patterned ground shields are compared against a predictive compact equivalent-circuit model. This model employs exact closed-form expressions for the inductances, and describes key performance figures such as characteristic impedance and attenuation loss with excellent accuracy     

A New Gate-Charging Protection Strategy for Transistors in Integrated-Circuit Test Chips and Products

This paper presents a new gate-charging protection strategy for transistors in integrated-circuit (IC) test chips and products. The strategy, using a low-threshold-voltage protection device (PD) of the highest voltage class (i.e., with the thickest available gate oxide) in any given process technology, is capable of providing full charging protection for transistors of all voltage classes during back-end plasma-involved manufacturing process. In conjunction with a method that globally turns off the PDs, the strategy also minimizes the protection-device-induced leakages during electrical tests or circuit operation. This new gate-charging protection strategy can benefit the design and manufacturing for the next-generation IC test chips and products, in particular for circuit products emphasized on low voltage and current and low power consumption.     

Coding and modulation for a horrible channel

Designing a system able to cope with a hostile channel is a typical challenge for data communication engineers. High-data-rate communication over power lines is an exemplar case: while power lines are a potentially convenient and inexpensive "no new wire" medium for data transmission, their features make it very difficult to design a simple modem. In this article we illustrate the main features of the power line communication channel, and some of the solutions advocated for modem design.     

4th power-law circuits using junction field-effect transistors

Several simple 4th power-law circuits compatible with current integrated-circuit technologies are presented. The circuits use matched symmetrical junction field-effect transistors and require no DC power supply     

并发双波段可重构功率放大器仿真设计

采用分布式PIN开关和并发双波段阻抗变换网络,实现了一种可重构高效率多波段功率放大器。与其他可重构放大器相比,该功率放大器降低了输出匹配电路的设计复杂度和开关对匹配电路的影响,有效节约了频谱资源,电路结构简单。双扇形开路微带线的使用拓展了高输入阻抗偏置电路的带宽。在进行匹配电路设计时,考虑了晶体管的寄生参数。仿真结果表明,该功率放大器具有高输出效率和良好的增益平坦度,验证了该方案的可行性。     

5. 8GHz 堆叠式功率放大器设计

基于2mm GaAs HBT 工艺,采用堆叠晶体管结构设计了一款5. 8GHz 功率放大器。通常堆叠式功率 放大器在高频情况下,上下两层晶体管间需要电感来完成功率匹配,在芯片设计中其电感会增加版图面积和级间功 耗,为此该设计则利用上层晶体管的基极与地之间的串联电阻、电容等效成堆叠结构级间的感性负载,从而减小了 级间的损耗与匹配难度。实测结果表明,该堆叠功率放大器在5. 8GHz 时增益为20. 6dB,饱和输出功率为29dBm,饱 和输出时功率附加效率达到36. 4%,芯片面积仅为1×0. 85mm2     

A wide-band operational amplifier with a new output stage and a simple frequency compensation

Innovations in circuit design have resulted in a high-performance wide band operational amplifier made by standard integrated-circuit production processes. A new class-B output circuit with very low distortion and high quiescent current stability a coupling method for differential amplifier stages incorporating the elimination of amplifier stages at high frequencies to obtain a first-order frequency response and an input stage combined with a level shift with lateral p-n-p transistors having capacitive feed forward to increase the bandwidth are used in this amplifier. A unity gain bandwidth of 50 MHz with an open-loop voltage gain of 3.10/SUP 5/ and an input bias current of 10 nA are obtained.     

Design of Millimeter-Wave Power Divider with Coupled Line

A novel 35GHz 3dB power divider using coupled transmission line is presented. Unlike conventional Wilkinson divider circuit, only the 50 Ω transmission lines are used in the design. The impedance matching can be achieved by coupled transmission line even mode characteristic impedance. The predicated and measured performances agree well.     

Analysis of Transmission Lines on Integrated-Circuit Chips

The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern of this paper. A lumped circuit model is proposed and justified on physical and experimental grounds. It is shown that interconnections behave like RC transmission lines at low frequencies, with the effect of inductance showing up at midrange and high frequencies. Some simple formulas are included for design use.     

A 150-MHz graphics rendering processor with 256-Mb embedded DRAM

A 150-MHz graphics rendering processor with an integrated 256-Mb embedded DRAM, delivering a rendering rate of 75 M polygons/s, is presented, 287.5 M transistors are integrated on a 21.3×21.7 mm ² die in a 0.18-μm embedded DRAM CMOS process with six layers of metal. Design methodologies for hierarchical electrical and physical design of this very large-scale IC, including power distribution, fully hierarchical timing design, and verification utilizing a newly developed nonlinear model, clock design, propagation delay, and crosstalk noise management in multi-millimeter RC transmission lines, are presented     

Comments on the emitter-current density dependence of popcorn noise frequency

It has been found that the power spectrum of popcorn noise in integrated-circuit transistors can extend well into the audio-frequency range even at low emitter-current densities.     

A Parallel-Strip Ring Power Divider With High Isolation and Arbitrary Power-Dividing Ratio

In this paper, a new power divider concept, which provides high flexibility of transmission line characteristic impedance and port impedance, is proposed. This power divider is implemented on a parallel-strip line, which is a balanced transmission line. By implementing the advantages and uniqueness of the parallel-strip line, the divider outperforms the conventional divider in terms of isolation bandwidths. A swap structure of the two lines of the parallel-strip line is employed in this design, which is critical for the isolation enhancements. A lumped-circuit model of the parallel-strip swap including all parasitic effects has been analyzed. An equal power divider with center frequency of 2 GHz was designed to demonstrate the idea. The experimental results show that the equal power divider has 96.5% -10-dB impedance bandwidth with more than 25-dB isolation and less than 0.7-dB insertion loss. In order to generalize the concept with an arbitrary power ratio, we also realize unequal power dividers with the same isolation characteristics. The impedance bandwidth of the proposed power divider will increase with the dividing ratio, which is opposite to the conventional Wilkinson power divider. Unequal dividers with dividing ratios of 1 : 2 and 1 : 12 are designed and measured. Additionally, a frequency independent 180 power divider has been realized with less than 2 phase errors.     

Square-law circuit using junction field-effect transistors

A simple square-law circuit which requires no DC power supply is proposed and experimentally demonstrated. The circuit uses a matched pair of symmetrical junction field-effect transistors, and is compatible with current integrated-circuit technologies     

宽带Wilkinson 功分器综合公式的缺陷与改进

首先介绍了3 种宽带Wilkinson 功分器的综合方法,重点阐述了最为常用的Cohn 的设计方法,并指出 随着功分器节数的不断增加,在利用Cohn 的设计公式计算隔离电阻阻值时会产生负数的问题。为此,通过引入一 个调整参数改进Cohn 的设计公式,实现了节数更多情况下隔离电阻阻值的准确计算。在计算功分器各级传输线特 性阻抗的过程中,提出了一种基于MATLAB 程序的多项式化简方法,实现了任意带宽的切比雪夫阻抗变换器参数的 快速计算。此外,还给出了一个8 级到15 级的功分器设计参数表格,作为对Cohn 给出的设计表格的扩展。最后,利 用改进后的设计公式,设计了一个1 ~15GHz 的宽带Wilkinson 功分器。仿真和测试结果证明了这种方法的有效性。     

Four-quadrant multiplier using junction field-effect transistors

A simple four-quadrant multiplier which requires no DC power supply is presented. The multiplication is ensured by four matched symmetrical junction field-effect transistors operating in the triode region. The circuit is compatible with current integrated-circuit technologies     

Cube-law circuit using junction field-effect transistors

A simple cube-law circuit compatible with current integrated-circuit technologies is presented. The circuit, which can operate as a frequency tripler if a single additional resistor is connected, uses several matched symmetrical junction field-effect transistors and requires no DC power supply     

Experimental evaluation of microwave field-effect-transistor noisemodels

Extensive GaAs field-effect-transistor noise measurements are used to compare noise models with the aim of recommending the most useful one for monolithic-microwave integrated-circuit design. The evaluation is based on noise and S-parameter measurements of metal-semiconductor field-effect transistors and high electron-mobility transistors with different gatewidths in the frequency range of 0.05-26 GHz. The models under investigation differ in the number of independent coefficients necessary to calculate the four noise parameters of the device. The broad frequency range including radio-frequency frequencies down to 50 MHz requires two different noise measurement systems with special modifications for optimum performance. In conclusion, the two-parameter Pospieszalski model turns out to be the most suitable one