Polyoxides grown on n+ polysilicon

The polarity asymmetry on the electrical characteristics of the oxides grown on n⁺ polysilicon (polyoxides) was investigated in terms of the oxidation process, the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that the thin polyoxide prepared by using a low-temperature wafer loading and N₂ pre-annealing process, has a smoother polyoxide/polysilicon interface and exhibits a lower oxide tunneling current, a higher dielectric breakdown field when the top electrode is positively biased, a lower electron trapping rate and a larger charge-to-breakdown than does the normal polyoxide. The polarity asymmetry is also strongly dependent on the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that only the thinner polyoxides (⩽240 Å) grown on the heavily-doped polysilicon film (30 Ω/sq) by using the higher-temperature oxidation process (⩾950°C) conduct a less oxide tunneling current when the top electrode is positively biased     

Field-enhanced tunneling and barrier lowering in Al—n+GaAs—nGaAs Schottky contacts grown by MBE

A thin, highly Si-doped (n-type) interfacial layer is used for controlled barrier lowering in n-type GaAs. The thickness and the doping density of the interfacial n+ layer in the range of 50-100 Å, are extracted from the measured electrical characteristics of Schottky contacts. A model for field-enhanced tunneling current in metal--nGaAs Schottky structures is presented and the experimental results for Al-n+ GaAs devices fabricated using molecular beam epitaxy (MBE) show good agreement.     

Noise in short n+-n--n+GaAs diodes

Noise measurements in a short, near-ballistic, n⁺-n^--n⁺GaAs diode are reported. The device had a linear characteristic below 100 mA. It showed1/fnoise at low frequencies and a white noise close to the thermal noise of the device conductancegat high frequencies. The1/fnoise is most likely mobility fluctuation noise; we evaluated Hooge's parameter α and found a value of 1.95 × 10^-6at room temperature and 0.959 × 10^-6at liquid nitrogen temperature. We also observed a1/fnoise spectrum turning over into1/f^0.5spectrum at 77 K.     

Bistable switching in supercritical n+-n-n+GaAs transferred electron devices

Bistable switching in supercritically doped n⁺-n-n⁺GaAs transferred electron devices (TED's) is investigated experimentally and interpreted in computer simulations, for which details of the computer program are given. Three switching modes all leading to stable anode domains are discussed, namely: 1) cathode-triggered traveling domain; 2) cathode-triggered accumulation layer; 3) anode-triggered domain. Relative current drops up to 40 percent, and switching times down to 60 ps are obtained in low-duty-cycle pulsed experiments with threshold currents around 400 mA. Optimum device parameters are shown to be as follows: 1) doping in the 3-4 × 10¹⁵cm^-3range; 2) length around 6 µm; 3) doping gradients below 20 percent; 4) high-quality interfaces.     

High-speed p+ GaInAs-n InP heterojunction JFET's(HJFET's) grown by MOCVD

The authors report the high-frequency characteristics of a new type of InP-JFET having p⁺ GaInAs as the gate material grown by MOCVD (metalorganic chemical vapor deposition) using tertiarybutylphosphine (TBP) and tertiarybutylarsine (TBA) as the alternative source for phosphine and arsine, respectively. Using selective wet chemical etching, heterojunction JFETs (HJFETs) with gate length of 0.6 μm led to a unity current gain cutoff frequency and power gain cutoff frequency of 14.3 and 37.5 GHz, respectively. The large valence band discontinuity (▵E_v≈0.37 eV) considerably suppresses hole injection into the channel in the HJFET as compared to homojunction InP-JFETs, making the HJFET a preferred device for high-speed logic circuits based on JFET technology     

Double-drift-region (p+pnn+) avalanche diode oscillators

The advantages of a double-drift-region avalanche diode oscillator are discussed. Conventional structures (p⁺nn⁺or n⁺pp⁺) are essentially single-drift-region devices in that transit-time delay (for IMPATT mode) and zone transit (for TRAPATT mode) occur in a single region of one impurity type. The proposed structure (p⁺pnn⁺) has two drift regions and is essentially two complementary avalanche diode oscillators in series.     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Voltage distribution in n+-n-n+and metal-cathode n-n+GaAs X-band oscillators using a SEM

Time-averaged and dynamic results have been obtained in n⁺-n-n⁺and metal cathode n-n⁺GaAsX-band devices, using a new voltage measurement scheme in the SEM. The n⁺-n-n⁺devices show accumulation layer propagation, and the metal-cathode devices show a trapped dipole domain behavior.     

Corner currents in p+-n-n+diodes with n+isolation diffusions

The magnitude of corner currents in rectangular diffused p⁺-n-n⁺diodes with deep n⁺isolation diffusions is discussed. Curves are given to illustrate the importance of this current in diodes and IIL structures.     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

The Hooge parameters of n+-p-n and p+-n-p silicon bipolar transistors

We establish here again the fact that the Hooge parameters of NEC57807 n⁺-p-n and in GE82 p⁺-n-p silicon bipolar transistors are orders of magnitude smaller than the value 2 × 10^-3postulated earlier. In the NEC57807 devices neither the base 1/fnoise nor the collector 1/fnoise is of the diffusion-fluctuation type. In the GE82 devices the collector 1/fnoise is not of the diffusion-fluctuation type, but the base 1/fnoise is of that type. We have given, also, a theory of the effects of surface recombination fluctuations in the emitter-base space-charge region on the base noise and the collector noise and find a noise spectrum that varies asI_gammawhere 0.5 < γ < 1.6 when going from small to large currents.     

Forward current—Voltage and switching characteristics of p+-n-n+(epitaxial) diodes

The forward-biased current-voltage and forward-to-reverse biased switching characteristics of p⁺-n-n⁺epitaxial diodes are investigated. The manner in which the n-n⁺junction affects the flow of injected minority carriers in the epitaxial region is characterized by a leakage parameter a. Experimentally, for diodes with epitaxial film widths much less than a diffusion length, a "box" profile accurately describes the injected minority carriers in the n region. The current is found to increase with increased epitaxial width at a fixed bias. A general switching expression for epitaxial diodes is presented and the validity of the expression is shown experimentally. The experimental values of a, determined independently from the current-voltage and switching characteristics, are in good agreement and show that the leakage of the high-low junction is dominated by the recombination of minority carriers in the n-n⁺space-charge region.     

Tunneling through ultrathin GaAs n++-p++-n++ barrier grown by molecular layer epitaxy

The I-V characteristics of ultrathin GaAs n⁺⁺-p⁺⁺ -n⁺⁺ barrier structures with a 45 Å thick p⁺⁺ layer grown by molecular layer epitaxy (MLE) have been measured at room temperature and 77 K. The tunneling probability for this structure has been calculated as a function of effective tunneling width. It was found that good agreement between experiment and calculation is obtained when the effective tunneling width is assumed to be 75 Å, which is much smaller than the depletion width about 190 Å measured by C-V method. This fact indicates that the depletion width approximation cannot be used to measure the exact tunneling width for ultrathin barrier devices     

Ultra-thin silicon-dioxide breakdown characteristics of MOS devices with n+and p+polysilicon gates

In this work we investigate the effect of the gate material on the breakdown characteristics of ultra-thin silicon dioxide films at low voltages (<6 V). When MOS capacitors are stressed with a positive gate voltage, the charge to breakdown and time to breakdown at a fixed oxide-voltage drop are significantly smaller in p+ polysilicon-gate capacitors than in n+ polysilicon-gate capacitors. The results are interpreted in terms of a simple model of hole tunneling resulting from hot-hole generation in the anode by hot electrons entering from the silicon dioxide. Extrapolation of high-voltage-breakdown lifetime measurements for relatively thick-oxide devices to low voltages may be complicated by this mechanism.     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

An As-P(n+-n-)double diffused drain MOSFET for VLSI's

An As-P(n⁺-n^-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10^-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.     

Self-aligned silicided (PtSi and CoSi2) ultra-shallow p+/n junctions

Ultra-shallow p+/n junctions (<100 nm) demonstrating excellent I-V characteristics have been fabricated with self-aligned PtSi. Junctions were formed by rapid thermal annealing (RTA) 〈100〉 Si preamorphized with Sn+ and implanted with BF2+. Subsequently, low-temperature RTA in N2of sputter-deposited Pt produced a 55-nm-thick PtSi layer possessing a remarkably smooth surface and interface, and demonstrating excellent resistance to the aqua regia etch solution. The silicided junctions displayed a sheet resistance of 14 Ω/sq with less than -2-nA . cm^-2reverse-bias leakage at -5 V. In a comparative scheme, similar junction characteristics were obtained using a self-aligned 39-nm-thick CoSi2overlayer.     

Spectral response of n+-n-p and n+-p photodiodes

Results of calculations for the quantum efficiency of three different types of n⁺-p, n⁺-n-p, and OCI-HLE diodes are reported. Exact numerical modeling of current density equations, modified to include bandgap reduction and Auger recombination is used to compute the quantum efficiency of these diodes. It is found that an optimized n⁺-p structure can result in over all spectral response comparable to the n⁺-n-p structure, although it is not as good as that of the OCI-HLE type of diodes. Further, these calculations show that one can achieve low dark current in these diodes, but at the expense of lower quantum efficiency particularly for wavelengths less than 0.4 µm.