A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.     

A power optimized 13-b 5 Msamples/s pipelined analog-to-digitalconverter in 1.2 μm CMOS

A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 μm CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply     

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm /spl times/ 1.4 mm.     

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.     

一种10位高速Pipeline-SAR混合型ADC设计

基于180 nm CMOS工艺,设计了一种无残差放大的10位100 MS/s流水线与逐次逼近混合型ADC。采用两级流水线-逐次逼近混合型结构,第一级完成4位粗量化转换,第二级完成6位细量化转换。为了降低整体电路功耗,采用单调式电容控制切换方式,两级之间残差电压采用采样开关电荷共享方式实现。采用异步时序控制逻辑,进一步提升了能量利用率和转换速度。后仿真结果表明,在100 MS/s奈奎斯特采样率下,有效位数为9.39 bit,信噪失真比为58.34 dB,1.8 V电源电压下整体功耗为5.9 mW。     

A 100-MS/s 8-b CMOS subranging ADC with sustained parametricperformance from 3.8 V down to 2.2 V

A 100-MS/s 8-b CMOS analog-to-digital converter (ADC) designed for very low supply voltage and power dissipation is presented. This single-ended-input ADC is based on the unified two-step subranging architecture, which processes the coarse and fine decisions in identical signal paths to maximize their matching. However, to minimize power and area, the coarse-to-fine overlap correction has been aggressively reduced to only one LSB. The ADC incorporates five established design techniques to maximize performance: bottom-plate sampling, distributed sampling, autozeroing, interpolation, and interleaving. Very low voltage operation required for a general purpose ADC was obtained with four additional and new circuit techniques. These are a dual-gain first-stage amplifier, differential T-gate boosting, a supply independent delay generator, and a digital delay-locked-loop controlled output driver. For a clock rate of 100 MS/s, 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained from 3.8 V down to 2.2 V. At 2.2 V, this 100-MS/s converter dissipates 75 mW plus 9 mW for the reference ladder. For a typical supply of 2.7 V, it consumes just 1 mW per MS/s over the 10-160-MS/s clock frequency range. Differential nonlinearity below 0.5 LSB is maintained from 2.7 V down to 2.2 V, and it degrades only slightly to 0.8 LSB at 3.8-V supply. The converter is implemented in a 0.35-μm CMOS process, with double-poly capacitors and no low-threshold devices     

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquistinput

This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-μm double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm² ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V     

A 1.2 V 12 b 60 MS/s CMOS Analog Front‐End for Image Signal Processing Applications

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front‐end (AFE) employing low‐power and flexible design techniques for image signal processing. An op‐amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog‐to‐digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 µm CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal‐to‐noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm² and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.     

Switched‐Capacitor Variable Gain Amplifier with Operational Amplifier Preset Technique

We present a novel operational amplifier preset technique for a switched‐capacitor circuit to reduce the acquisition time by improving the slewing. The acquisition time of a variable gain amplifier (VGA) using the proposed technique is reduced by 30% compared with a conventional one; therefore, the power consumption of the VGA is decreased. For additional power reduction, a programmable capacitor array scheme is used in the VGA. In the 0.13 μm CMOS process, the VGA, which consists of three‐stages, occupies 0.33 mm² and dissipates 19.2 mW at 60 MHz with a supply voltage of 1.2 V. The gain range is 36.03 dB, which is controlled by a 10‐bit control word with a gain error of ±0.68 LSB.     

A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs

A pseudo-background continuous-time strategy is developed for gain and offset calibration in open-loop inter-stage residue amplifiers of pipeline ADCs. The ping-pong calibration strategy is enhanced for loop gain and accuracy to be utilized for open-loop RAs. Thanks to a reliable technique for preserving analog voltages for long time durations, data conversion continuously proceeds. In addition, other advantages of the foreground techniques, like lower power consumption and smaller area are achieved. The reduction in power consumption due to the elimination of a wide-bit digital processor easily overcomes the increase which stems from the replica residue amplifier. Storing the calibration results in reliable analog storages, the multiplexing frequency and clock frequency within the calibration loop are reduced to 100 KHz, respectively, which result in a significant amount of power reduction. Monte-Carlo analysis for 100 iterations shows that the calibration loop provides an absolute gain of 4 with the median value of 3.996 and standard deviation of 0.003, while the threshold voltages and reference levels experience a Gaussian distribution with 25 mV variations at 3σ. Total power consumption equals 1.8 mW for both the offset and gain calibration at 1.8 V (and 3.3 V for DAC) supply voltage. More than 9-bit accuracy is obtained at 50 mV peak-to-peak residue. Linearity is reduced to 7-bits for full-swing input range. Also, 13 dB and 8 dB improvement in SNDR and SFDR of a 13-bit 100S/s pipeline ADC is achieved when the offset and gain calibration loops are activated. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 μm CMOS technology.     

A $$3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}$$ rail-to-rail operational amplifier in silicon-on-sapphire with constant transconductance

This paper presents the design, fabrication, and electrical measurement results from a low-noise high-performance amplifier fabricated in the 0.5 μm silicon-on-sapphire (SOS) technology. The amplifier was designed with rail-to-rail input and output swing and constant transconductance in its entire common-mode range and targets biomedical instrumentation in SOS/SOI technologies. The amplifier reports \(3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}\) of input-referred voltage noise at 10 kHz and has 0.4 mV of input-referred offset. The gain-bandwidth product of the amplifier is 12 MHz and the open-loop gain is 75 dB. The amplifier occupies 0.08 mm² of area and consumes 1.4 mW of power.     

A low power and small area digital self-calibration technique for pipeline ADC

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5 μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1 mW and 1.05 mm², respectively. At a sampling rate of 30 MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25 MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1 dB and 52.1 dB to 75.51 dB and 83.61 dB, respectively. The 12.25 effective number of bits at 30 MS/s ADC consumes a total power of 136 mW.     

A 2-V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-μm CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-μm CMOS technology, without tuning or trimming     

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the...     

An 8-bit 150-MHz CMOS A/D converter

This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-μm CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2×1.5 mm²     

A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC

A low voltage-power, 13-bit and 16 MSPS analog-to-digital converter (ADC) was implemented in 0.25-/spl mu/m one-poly five-metal standard CMOS process with MIM capacitors. This ADC used a constant-gm switch to improve the nonlinear effect and a telescopic operational transconductance amplifier with a wide-swing biasing technique for power saving and low supply voltage operation. The converter achieved a peak SNDR of 59.2 dB with 16.384 MSPS, a low supply voltage of 1.3V, and Nyquist input frequency of 8.75 MHz. The static INL of /spl plusmn/2.0 LSB and DNL of /spl plusmn/0.5 LSB were obtained. The total power consumption of this converter was 78 mW. This chip occupied 3.4 mm /spl times/ 3.6 mm area.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

A 100-MHz CMOS DAC for video-graphic systems

A 6-b weighted-current-sink video digital-to-analog converter (DAC) with 10-90% rise/fall time of 4 ns, integrated with a double-metal 3-μm CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technology. Experimental results show that a conversion rate of 100 MHz is achievable. The power consumption is 150 mW and the active chip area is 0.5×1.0 mm² . The differential of 0.1 LSB demonstrates that 8 b of accuracy can be achieved. The integral linearity is 0.5 LSB     

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.     

A 15-b, 5-Msample/s low-spurious CMOS ADC

A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit (MSB) stages are digitally calibrated to implement a 15-b, 5-Msample/s low-spurious ADC using 1.4-μm CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC's in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components are suppressed to below -93 dB when sampled at 5 MHz. The chip occupies 27 mm², and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing