On the InGaP/GaAs/InGaAs camel-like FET for high-breakdown,low-leakage, and high-temperature operations

A new field-effect transistor using a high-barrier n⁺ -GaAs/p⁺-InGaP/n-GaAs camel-like gate and GaAs/InGaAs heterostructure-channel has been fabricated successfully and demonstrated. Experimentally, an ultra high gate-drain breakdown voltage of 52 V, a high drain-source operation voltage over 20 V with low leakage currents, and a high drain-source off-state breakdown voltage of 39.7 V are obtained for a 1×100 μm² device. The high breakdown behavior is attributed to the use of high barrier camel-like gate and heterostructure channels to reduce the undesired leakage current. Furthermore, the studied device also shows high breakdown behavior in a high temperature environment and good microwave characteristics. Therefore, based on these characteristics, the studied device is suitable for high-breakdown, low-leakage, and high-temperature applications     

100 Å-thick tunnel junction by double impurity doping liquid phase epitaxy for V-band TUNNETT oscillation

The tunnel injection transit time (TUNNETT) diodes with p⁺p⁺n⁺n⁻n⁺ structure were fabricated by liquid phase epitaxy (LPE). About 100 Å tunnel junction (p⁺n⁺) was successfully prepared by the double impurity diffusion of Ge and S during LPE growth. Continuous wave (CW) oscillation was realized at 51.520 GHz in the V-band cavity with the phase noise of −60 dBc/Hz at 1 kHz bandwidth.     

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ?m² six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm² bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.     

DC characteristics of high-breakdown-voltage p-i-n diodes made by20-MeV Si implantation in InP:Fe

A vertical p-i-n diode is made for the first time in InP:Fe using megaelectronvolt energy ion implantation, A 20-MeV Si implantation and kiloelectronvolt energy Be/P coimplantation are used to obtain a buried n⁺ layer and a shallow p⁺ layer, respectively. The junction area of the device is 2.3×10^-5 cm² and the intrinsic region thickness is ≈3 μm. The device has a high breakdown voltage of 110 V, reverse leakage current of 0.1 mA/cm² at -80 V, off-state capacitance of 2.2 nF/cm² at -20 V, and a DC incremental forward resistance of 4 Ω at 40 mA     

Investigation of temperature-dependent characteristics of ann+-InGaAs/n-GaAs composite doped channel HFET

The temperature-dependent characteristics of an n⁺-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor (HFET) have been studied. Due to the reduction of leakage current and good carrier confinement in the n ⁺-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1×100 μm² device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. The shift of V_th from 300 to 450 K is only 13 mV. In addition, the studied device also shows good microwave performances with flat and. wide operation regime     

Photosensitive pulse oscillator

A new type of semiconductor photosensitive device has been developed, differing from photodetectors used hitherto in the characteristics and the operation mechanism of the device. In the present device, stable oscillation is observed in the (n⁺-p⁺- n-n⁺)-p⁺structure of silicon in the applied voltage range, two ∼ several hundred volts, with illumination above a threshold light intensity. The oscillation frequency increases linearly with the light intensity. For instance, with variation of light intensity 0.1 mW, the frequency changes by 3.6 kHz for the applied voltage of 30 V. With increasing applied voltage, the threshold light intensity and the oscillation frequency decrease. The frequency is expressed byA(L - 0.05)V_{a}^{-0.64}which agrees well with the experimental results. With rising temperature, the frequency varies little though the threshold light intensity decreases. The large output peak power of oscillation (12.5 W at 100 V) is obtained. In this paper, the fundamental characteristics and the operation mechanism of the device are presented.     

4H-SiC TSOB结势垒肖特基二极管静态特性

为增强器件的反向耐压能力,降低器件的漏电功耗,采用Silvaco TCAD对沟槽底部具有SiO₂间隔的结势垒肖特基二极管(TSOB)的器件特性进行了仿真研究。通过优化参数来改善导通压降(V_F)-反向漏电流(I_R)和击穿电压的折衷关系。室温下,沟槽深度为2.2 μm时,器件的击穿电压达到1 610 V。正向导通压降为2.1 V,在V_F=3 V时正向电流密度为199 A/cm²。为进一步改善器件的反向阻断特性,在P型多晶硅掺杂的有源区生成一层SiO₂来优化漂移区电场分布,此时改善的器件结构在维持正向导通压降2.1 V的前提下,击穿电压达到1 821 V,增加了13%。在1 000 V反向偏置电压下,反向漏电流密度比普通结构降低了87%,有效降低了器件的漏电功耗。普通器件结构的开/关电流比为2.6×10³(1 V/-500 V),而改善的结构为1.3×10⁴(1 V/-500 V)。     

A novel trench termination design for 100-V TMBS diode application

In this letter, a novel trench termination structure that can inhibit the reverse leakage current substantially and reduce the process cost is introduced. For trench type power devices, such as trench MOS barrier Schottky (TMBS) diodes, this new termination structure can be processed simultaneously with the active region without any additional mask. Simulation and experimental results show that TMBS diodes with this new termination structure can achieve a reverse blocking voltage of 100 V with a leakage current density as low as 8.4×10^-4 A/cm²     

Enhancement-mode power heterojunction FET utilizingAl0.5Ga0.5As barrier layer with negligibleoperation gate current for digital cellular phones

We have developed a novel enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET (HJFET) with a 5 nm thick Al_0.5Ga_0.5As barrier layer inserted between an In _0.2Ga_0.8As channel layer and an upper Al_0.2 Ga_0.8As electron supply layer. The Al_0.5Ga _0.5As barrier layer reduces gate current under high forward gate bias voltage, resulting in a high forward gate turn-on voltage (V _F) of 0.87 V, which is 170 mV higher than that of an HJFET without the barrier layer. Suppression of gate current assisted by a parallel conduction path in the upper electron supply layer was found to be also important for achieving the high V_F. The developed device exhibited a high maximum drain current of 300 mA/mm with a threshold voltage of 0.17 V. A 950 MHz PDC power performance was evaluated under single 3.5 V operation. An HJFET with a 0.5 μm long gate exhibited 0.92 W output power and 63.6% power-added efficiency with 0.08 mA gate current (I_g) at -48 dBc adjacent channel leakage power at 50 kHz off-center frequency. This I_g is one-thirteenth to that of the HJFET without the barrier layer. These results indicate that the developed enhancement-mode HJFET is suitable for single low voltage operation power applications     

A CMOS compatible lateral emitter switched thyristor with enhancedturn-on capability

A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n^- drift region and the n⁺ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3 μm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm² with 5 V gate voltage     

Anisotype-gate self-aligned p-channel heterostructure field-effecttransistors

A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded n⁺ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60 Å, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3×10 μm PFETs, high reverse breakdown voltages 9-10 V, and low capacitance. Microwave S -parameter characterization resulted in F_t of 5 GHz for a 1×50 μm PFET     

Low voltage circuit design techniques for battery-operated and/orgiga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q_s) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm² and cell size is 1.35×2.8 μm²     

Low Subthreshold Swing HfLaO/Pentacene Organic Thin-Film Transistors

We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of -1.3 V, and a field-effect mobility of 0.71cm²/ Vldrs . This occurred along with an ON-OFF state drive current ratio of 1.0 times 10⁵, when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm² that is given by the HfLaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 times 10^-7 at 2 V.     

High performance pseudomorphic InGaP/InGaAs power HEMTs

Power transistors with a low d.c. supply voltage were demonstrated with pseudomorphic InGaP/In_0.2Ga_0.8As/GaAs heterostructure field effect transistors on GaAs substrates and 1 μm gate length technology. A current density of 200 mA mm⁻¹ and an extrinsic transconductance of 300 mS mm⁻¹ were exhibited on a 400 μm gate width process control monitor device. For a 1 cm gate width device measured at 850 MHz and V_ds = 1.3 V, state-of-the-art results, 57.4% for the PAE, 12.7 dB for the linear gain and 21.5 dBm for the output power, were obtained.     

A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum² low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.     

Performance comparison of highly integrated circuits: Silicon NMOS versus gallium arsenide normally-off MESFET technology

This study presents a performance comparison between highly integrated circuits on gallium arsenide and on silicon realized with normally-off MESFET's and n-channel MOSFET's, respectively. As a basis, a standard cell structure is chosen in order to obtain a realistic capacitive loading. This cell is scaled down twice from an area of 1 mm²to 0.38 mm²and to 0.13 mm². The corresponding effective gate length inside the cell is 1, 0.5, and 0.2 µm, respectively. The delay time of a loaded inverter, the power consumption as well as the power-delay product are calculated using device parameters deduced from experimentalI-Vcharacteristics. For MOSFET's good noise margins at low switching times are obtained at a supply voltage of 3 V. The GaAs circuit exhibits a lower power consumption by one order of magnitude and a smaller delay time by about a factor of 2. Since nonoptimized GaAs MESFET's with recessed gates were regarded for the comparison improvements are expected for self-aligned MESFET's. For a supply voltage of 1 V, the MOSFET circuit shows a comparable power consumption to the GaAs circuit but longer delay time (factor 2 to 5).     

基于STM32的直流稳压电源及漏电保护装置

基于STM32的直流稳压电源及漏电保护装置由三大部分组成,分别是直流稳压电源模块、漏电保护模块和显示模块.稳压电源模块采用具有放大环节的串联型稳压电路,电路结构简单,输出电压稳定、输出电流大.漏电保护装置采用INA195,该芯片能灵敏的检测到漏电电流是否超出预定指标.显示电路采用NOKIA5110进行参数显示,在低功耗、低成本的条件下,实现人机交换.经过测试该电源运行稳定.     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p⁺-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10^-7Ω-cm²), and high channel mobility (620 and 210 cm²/V . s).     

Amorphous-Si emitter heterojunction UHF power transistors for handytransmitter

A UHF silicon heterojunction bipolar power transistor with a heavily doped amorphous-silicon emitter is reported. The fabrication process utilized an improved glow discharge technique. The deposition rate of amorphous silicon is 0.3-0.4 Å/s, which is slower than that of conventional a-Si:H. The average carrier density in the amorphous-silicon film is estimated to be about 1.5×10¹⁹ cm^-3. The present device can deliver 4.0-W output power with 72% collector efficiency and 8.2-dB gain at 470 MHz for 9.0-V low supply voltage. These preliminary results make the use of n⁺ a-Si:H as a wide-bandgap emitter material for high-frequency and high-power heterojunction bipolar transistors (HBTs) very attractive