Self-aligned p-channel MISFET with a low-temperature-grown GaAsgate insulator

A new p-channel GaAs metal-insulator-semiconductor field-effect transistor (MISFET) using low-temperature-grown (LTG) GaAs as the gate insulator is demonstrated. Neither the GaAs conducting channel nor the gate insulator was doped, and a Be self-aligned implant was used to lower the source and drain series resistance. For a MISFET with a 1.5-μm gate length, the transconductance is 22 mS/mm and the maximum drain current is 120 mA/mm obtained at -8 V of gate bias. The measured unity-current-gain cut-off frequency f_T is 2.0 GHz     

Sulfide treated GaAs MISFET's with gate insulator of photo-CVDgrown P3N5 film

Sulfide passivated GaAs MISFET's with the gate insulator of photo-CVD grown P₃N₅ films have been successfully fabricated. The device shows the drain current instability less than 22% for the period of 1.0 s ~1.0×10⁴ s, due to excellent properties of sulfide treated P₃N₅/GaAs interface. The effective electron mobility and extrinsic transconductance of the device are about 1300 cm²/V·sec and 1.33 mS, respectively, at room temperature. To estimate the effects of sulfide treatment on P₃N₅/GaAs interfacial properties, GaAs-MIS diodes are also fabricated     

An all implanted self-aligned enhancement mode n-JFET with Zn gatesfor GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p⁺ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p⁺/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f_t of 19 GHz with an f_max of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits     

Characterization of double pulse-doped channel GaAs MESFETs

The fabrication and characterization of a double pulse-doped (DPD) GaAs MESFET grown by organometallic vapor phase epitaxy (OMVPE) are reported. The electron mobility of a DPD structure with a carrier concentration of 3×10¹⁸/cm³ was 2000 cm²/V-s, which is about 20% higher than that of a pulse-doped (PD) structure. Implementing the DPD structure instead of the conventional PD structure as a GaAs MESFET channel, the drain breakdown voltage, current gain cutoff frequency, and maximum stable gain (MSG) increase. The maximum transconductance of 265 mS/mm at a drain current density of 600 mA/mm, a current gain cutoff frequency of 40 GHz, and an MSG of 11 dB at 18 GHz were obtained for a 0.3 μm n⁺ self-aligned DPD GaAs MESFET     

New self-aligned T-gate InGaP/GaAs field-effect transistors grownby LP-MOCVD

This paper reports on self-aligned T-gate InGaP/GaAs FETs using n ⁺/N⁺/δ(P⁺)/n structures. N⁺ -InGaP/δ(P⁺)-InGaP/n-GaAs forms a planar-doped barrier. The inherent ohmic gate of camel-gate FETs together with a highly selective etch between an InGaP and a GaAs layers offers a self-aligned T-shape gate with a reduced effective length. A fabricated device with a reduced gate dimension of 1.5×100 (0.6×100) μm² obtained from 2×100 (1×100) μm² gate metal exhibits an extrinsic transconductance, unity-current gain frequency, and unity-power gain frequency of 78 (80) mS/mm, 9 (19.5), and 28 (30) GHz, respectively     

Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

High-transconductance p-channel AlGaAs/GaAs HFETs with low-energyberyllium and fluorine co-implantation self-alignment

The fabrication and electrical characteristics of p-channel AlGaAs/GaAs heterostructure FETs with self-aligned p⁺ source-drain regions formed by low-energy co-implantation of Be and F are reported. The devices utilize a sidewall-assisted refractory gate process and are fabricated on an undoped AlGaAs/GaAs heterostructure grown by MOVPE. Compared with Be implantation alone, the co-implantation of F⁺ at 8 keV with 2×10¹⁴ ions/cm² results in a 3× increase in the post-anneal Be concentration near the surface for a Be⁺ implantation at 15 keV with 4×10¹⁴ ions/cm². Co-implantation permits a low source resistance to be obtained with shallow p⁺ source-drain regions. Although short-channel effects must be further reduced at small gate lengths, the electrical characteristics are otherwise excellent and show a 77-K transconductance as high as 207 mS/mm for a 0.5-μm gate length     

An all-implanted, self-aligned, GaAs JFET with a nonalloyedW/p+-GaAs ohmic gate contact

We describe a self-aligned, refractory metal gate contact, enhancement mode, GaAs junction field effect transistor (JFET) where all impurity doping was done by ion implantation. Processing conditions are presented for realizing a high gate turn-on voltage (~1.0 V at 1 mA/mm of gate current) relative to GaAs MESFET's. The high gate turn-on voltage is the result of optimizing the p⁺-gate implant and anneal to achieve a nonalloyed ohmic contact between the implanted p⁺-GaAs and the sputter deposited tungsten gate contact. Initial nominally 1.0 μm×50 μm n-JFET's have a transconductance of 85 mS/mm and f_t of 11.4 GHz     

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 10¹²eV^-1. cm^-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

Gigahertz logic gates based on InP-MISFET's with minimal drain current drift

Three-input AND/NOR logic gates based on 3-µm overlapping gate InP-MISFET technology were fabricated and clocked at 1 GHz. The logic gates showed a propagation delay of ∼500-700 pS/gate for a channel length of 1.5 µm. Such high-speed performance was obtainable as a result of a novel process that was used in the fabrication of the MISFET's. The process included the saturation of InP surface with phosphorus vapor and growth of a P2OxN1-xinterfacial layer followed by the deposition of an SiO2gate insulator. MISFET's that were utilized in the logic gates showed a channel mobility of ∼3700 cm²/V.s and less than 3-percent drain current drift.     

A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is proposed and experimentally demonstrated. The unique feature of the technology is the formation of self-aligned and symmetrical lightly doped source/drain (LDD) structure without any additional photolithographic or implantation steps. Thus, the number of masks used in the technology is the same as that in a conventional top gate TFT technology. Moreover, devices formed by the proposed method have thick source/drain and a thin channel region for providing low source/drain resistance and improved I-V characteristics. P-channel TFT devices are fabricated using a simple low temperature (⩽600°C) process. The fabricated SABG-TFT exhibits symmetrical transfer characteristics when the polarity of source/drain bias is reversed. The effective mobility and on-off current ratio of the devices are about 35 cm²/V-s and 6×10⁶ respectively     

A new self-aligned GaAs FET with a Mo/WSixT-gate

An n+-layer and ohmic electrode self-aligned (NOSA) GaAs FET is a new self-aligned GaAs FET in which n⁺-layers and ohmic contacts in the source and the drain regions are self-aligned to a T-shaped gate formed with Mo and WSix(≈0.6) double layers. Using the NOSA FET structure, the device area can be easily reduced because no alignment margin is needed. The fabricated FET's exhibit a transconductance gmof 170 mS/mm.     

A 0.4-μm gate-length AlGaAs/GaAs P-channel HIGFET with 127-mS/mmtransconductance at 77 K

WN-gate, p-channel AlGaAs-GaAs heterostructure insulated-gate field-effect transistors (HIGFETs) fabricated on a metalorganic vapor-phase epitaxy (MOVPE) wafer are discussed. A self-aligned Mg ion implantation (80 keV, 6×10¹³ cm^-2) annealed at 850°C in an arsine atmosphere and the control of the SiO₂ sidewall dimensions allow the fabrication of p-channel HIGFETs with a gate length smaller than 0.5 μm with low subthreshold current. P-channel HIGFETs with 0.4-μm gate lengths exhibit extrinsic transconductances as high as 127 mS/mm at 77 K and 54 mS/mm at 300 K     

High-performance Ga0.51In0.49P/GaAs airbridgegate MISFET's grown by gas-source MBE

Ga_0.51In_0.49P/GaAs MISFET's, in which Ga_0.51In_0.49P insulating layer was inserted between the gate metal and the channel layer, were compared with MESFET's experimentally and theoretically in terms of DC and microwave performance. Devices performance were evaluated by varying the thickness of the insulating layer. Wide and flat characteristics of g_m, g_t, and f_max versus drain current (or gate voltage) together with a high maximum current density (above 610 mA/mm) were achieved for devices with insulating layer thickness of 50 mn and 100 mm. Moreover, the maximum values of J_t's and f_max 's for a 1-μm gate length device both occurred when t was between 50 and 100 mn. We also observed that parasitic capacitances and gate leakage currents were minimized by using the airbridge gate structure, and thus high-frequency and breakdown characteristics were greatly improved, These results demonstrate that Ga_0.51In_0.49P/GaAs airbridge gate MISFET's with insulating layer thickness between 50 and 100 mn were very suitable for microwave high-power device applications     

Integration of GalnP/GaAs heterojunction bipolar transistors andhigh electron mobility transistors

Integration of carbon-doped GaInP/GaAs heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs) is demonstrated by growing an HBT on the top of a HEMT. A current gain of 60, a cutoff frequency of 59 GHz and a maximum oscillation frequency of 68 GHz were obtained for a 5×15 μm² self-aligned HBT. The HEMT, with a gate length of 1.5 μm has a transconductance of 210 mS/mm, a cutoff frequency of 9 GHz and a maximum oscillation frequency of 22 GHz. It is shown that the GaInP/GaAs HBT on the HEMT is a simple Bi-FET technology suitable for microwave and mixed signal applications     

An amorphous silicon thin-film transistor with fully self-alignedtop gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm² V^-1 s^-1, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm² V^-1 s^-1, in the saturated region and 0.5 cm² V ^-1 s^-1, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.     

Heterostructure devices using self-aligned p-type diffused ohmiccontacts

Describes the use of a p-type refractory ohmic contact in ohmic self-aligned devices. The contacts are based on self-aligned diffusion of zinc-doped tungsten film. The diffusion is nearly isotropic in the vicinity of silicon nitride sidewalls, allowing self-alignment of ohmic contacts with emitters and gates. Low-resistance contacts (<10^-6 Ω·cm²) are formed both to GaAs and GaAlAs, and the lifetime of the diffused region is superior to that obtained from implantation. Heterostructure bipolar transistors (HBTs) showing high current gains (⩾50 at 2×10³ A·cm^-2 and ⩾200 at 1×10⁵ A·cm^-2 with micrometer-sized emitter widths) and p-channel GaAs gate heterostructure field-effect transistors (HFETs) showing high transconductances (78 mS/mm at 2.2-μm gate length) have been fabricated using this contact