Niobium-based integrated circuit technologies

Metallurgical and electrical properties of Nb and NbN films for use as Josephson junction electrodes and wiring layers are investigated. The crystallographic and superconducting properties necessary for Nb-based integrated circuit processes are clarified. Tunnel barrier structures of NbN-Nb oxide-NbN (Pb alloy) and Nb-Al oxide-Nb Josephson junctions have been analyzed and correlated with junction characteristics and critical current uniformity. It was found that the surface structure of a base electrode should be smooth to ensure that Josephson junctions have low leakage current and uniform critical current distribution. New types of Josephson junctions with artificial tunnel barriers such as amorphous Si or Mg oxide are reviewed. A variety of Josephson junction structures or processes have been developed for Nb-based Josephson integrated circuits in order to improve circuit performance. These include junction miniaturization, planarization, and stacked junction structures. These structures are mainly intended for Nb-Al oxide-Nb Josephson circuits. The Nb-Al oxide-Nb Josephson junction technology is by far the most advanced and has been used in logic and memory circuits, for example a 4-bit×4-bit parallel multiplier, a Josephson logic gate array, a 16-bit arithmetic logic unit, a 4-bit microprocessor, and 1-kb and 4-kb memory circuits     

Superconductor analog-to-digital converters

Ultrafast switching speed, low power, natural quantization of magnetic flux, quantum accuracy, and low noise of cryogenic superconductor circuits enable fast and accurate data conversion between the analog and digital domains. Based on rapid single-flux quantum (RSFQ) logic, these integrated circuits are capable of achieving performance levels unattainable by any other technology. Two major classes of superconductor analog-to-digital converters (ADCs) are being developed - Nyquist sampling and oversampling converters. Complete systems with digital sampling at rates of /spl sim/20 GHz and above have been demonstrated using low-temperature superconductor device technology. Some ADC components have also been implemented using high-temperature superconductors. Superconductor ADCs have unique applications in true digital-RF communications, broadband instrumentation, and digital sensor readout. Their designs, test results, and future development trends are reviewed.     

InGaAs-InP DHBTs for increased digital IC bandwidth having a 391-GHz f/sub /spl tau// and 505-GHz f/sub max/

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz f/sub /spl tau// and 505-GHz f/sub max/, which is the highest f/sub /spl tau// reported for an InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance C/sub cb/. In addition, the base sheet resistance /spl rho//sub s/ along with the base and emitter contact resistivities /spl rho//sub c/ have been lowered. The dc current gain /spl beta/ is /spl ap/36 and V/sub BR,CEO/=5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from f/sub clk/=3 to 142.0 GHz while dissipating /spl ap/800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

High-Speed Si-Bipolar and GaAs Technologies

Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advancement of the device technology. GaAs int&égrated circuit technologies have rapidly developed over the last few years so that both analog and digital integrated circuits are now commercially available. These circuits all use the GaAs MESFET as the basic switching or modulating transistor. Integrated circuits based on more sophisticated heterostructure components, such as the heterojunction bipolar transistor or the modulation doped FET, are currently being developed. This paper will try to give an overview of present state of the art high-speed silicon bipolar technology and compare it to competing GaAs technologies. The most recent advances in oxide isolation technology which have led to the availability of 2.6 GHz dividers and the trend to self-aligned processes which can be used to achieve even smaller geometries will be described. On the GaAs side, the various GaAs-MESFET logic technologies and the heterojunction transistor technologies will be looked at regarding their present status and what can be expected in the near future. Most of the data will relate to monolithically integrated frequency dividers where a requirement for higher input frequencies combined with low power consumption exists.     

InP Bipolar ICs: Scaling Roadmaps, Frequency Limits, Manufacturable Technologies

Indium phosphide heterojunction bipolar transistors (HBTs) find applications in very wide-band digital and mixed-signal integrated circuits (ICs). Devices fabricated in high-yield process flows at 500 nm feature size obtain 450 GHz cutoff frequencies and 5 V breakdown and enable high yield fabrication of integrated circuits having more than 3000 transistors. Laboratory devices at 250 nm feature size obtain 755 GHz . We describe device and circuit bandwidth limits associated with HBTs, develop scaling roadmaps for HBTs having lithographic minimum feature sizes between 512 and 64 nm, and identify key technological challenges in realizing 480-GHz digital ICs and 1000-GHz amplifiers. Key features of manufacturable self-aligned dielectric sidewall processes are described in detail.     

High-Speed GaAs SDFL Divider Circuit

High-speed divider circuits find numerous applications in prescalers for counters, frequency synthesizers, and digital phase locked loops. To accommodate these applications, a high-speed multimode divider circuit has been designed, fabricated, and tested. This circuit, fabricated on semi-insulating Gallium Arsenide substrates, and utilizing Schottky diode FET logic (SDFL) technology, has been tested at a maximum clock frequency of 1.84 GHz. High yields of circuits operating over 1 GHz have been obtained over a number of wafers.     

High-speed GaAs SDFL divider circuit

High-speed divider circuits find numerous applications in prescalers for counters, frequency synthesizers, and digital phase locked loops. To accommodate these applications, a high-speed multimode divider circuit has been designed, fabricated, and tested. This circuit, fabricated on semi-insulating Gallium Arsenide substrates, and utilizing Schottky diode FET logic (SDFL) technology, has been tested at a maximum clock frequency of 1.84 GHz. High yields of circuits operating over 1 GHz have been obtained over a number of wafers.     

A flat-panel display control IC with 150-V drivers

A flat-panel display control IC with 150-V drivers is realized in high-voltage analog/digital IC technology utilizing a low-cost p-n junction isolation process. An improved semiwell isolation structure that has an epitaxial layer of two different thicknesses is used. In order to achieve high-voltage push-pull operation, totem-pole-type output circuits are formed in the structure's thick, high-resistivity epitaxial area. A compact complementary transistor logic circuit is successfully integrated in the n-wells of the structure's thin epitaxial area to meet the high-speed requirement for control logic. A stacked circuit is used to reduce the standby power needs of the logic circuits.     

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (tau_{d} sim 100ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low astau_{d} = 110ps).     

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.     

Monte Carlo optimization of superconducting complementary outputswitching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix     

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130 nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits.     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

Transistor and circuit design for 100-200-GHz ICs

Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f/sub /spl tau// and 490 GHz f/sub max/ DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C/sub cb/, and emitter junction regrowth for reduced base and emitter resistances.     

GaAs digital IC technology/statistical analysis of device performance

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.     

Timing circuits for RSFQ digital systems

A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm². The most complex clock controller generates trains of 2²⁴ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6×10^-5 . The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz     

Superconducting digital electronics

Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.