Robust learning controller design for MIMO stochastic discrete‐time systems: An H∞‐based approach

This paper is devoted to designing iterative learning control (ILC) for multiple‐input multiple‐output discrete‐time systems that are subject to random disturbances varying from iteration to iteration. Using the super‐vector approach to ILC, statistical expressions are presented for both expectation and variance of the tracking error, and time‐domain conditions are developed to ensure their asymptotic stability and monotonic convergence. It shows that time‐domain conditions can be tied together with an H_∞‐based condition in the frequency domain by considering the properties of block Toeplitz matrices. This makes it possible to apply the linear matrix inequality technique to describe the convergence conditions and to obtain formulas for the control law design. Furthermore, the H_∞‐based approach is shown applicable to ILC design regardless of the system relative degree, which can also be used to address issues of model uncertainty. For a class of systems with a relative degree of one, simulation tests are provided to illustrate the effectiveness of the H_∞‐based approach to robust ILC design. Copyright © 2011 John Wiley & Sons, Ltd.     

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd.