Series resonant ZCS‐PFM DC‐DC power converter with high‐frequency high‐voltage transformer link for high‐power magnetron drive

This paper presents a single lossless inductive snubber‐assisted ZCS‐PFM series resonant DC‐DC power converter with a high‐frequency high‐voltage transformer link for industrial‐use high‐power magnetron drive. The current flowing through the active power switches rises gradually at a turned‐on transient state with the aid of a single lossless snubber inductor, and ZCS turn‐on commutation based on overlapping current can be achieved via the wide range pulse frequency modulation control scheme. The high‐frequency high‐voltage transformer primary side resonant current always becomes continuous operation mode, by electromagnetic loose coupling design of the high‐frequency high‐voltage transformer and the magnetizing inductance of the high‐frequency high‐voltage transformer. As a result, this high‐voltage power converter circuit for the magnetron can achieve a complete zero current soft switching under the condition of broad width gate voltage signals. Furthermore, this high‐voltage DC‐DC power converter circuit can regulate the output power from zero to full over audible frequency range via the two resonant frequency circuit design. Its operating performances are evaluated and discussed on the basis of the power loss analysis simulation and the experimental results from a practical point of view. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 153(3): 79–87, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20126     

A waveform generator circuit for extra low‐frequency CMOS micro‐power applications

This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.     

Phase‐Locked Loop Using Complex‐Coefficient Filters for Grid‐Connected Inverter

Recently, photovoltaic (PV) power systems have attracted considerable attention in attempts to mitigate global warming. In a PV power system, it is necessary to synchronize the grid voltage when a PV inverter is interconnected with a grid. This paper proposes a high‐speed and high‐precision phase‐locked loop (PLL) using complex‐coefficient filters for a single‐phase grid‐connected inverter. The proposed PLL can detect the phase of grid voltage that has superimposed harmonic components for grid fault. Moreover, numerical results show the effectiveness of the proposed method.     

High‐efficiency grid‐connected inverter topology for low‐power photovoltaic applications

For low‐power applications, such as household photovoltaic panels, the efficiency and reliability of the distributed generation system is an important issue. A high‐efficiency inverter topology derived from the normal full‐bridge circuit is proposed for grid‐connected photovoltaic applications. In the proposed topology, a couple of diodes are added in parallel with the grid‐frequency switches as freewheeling diodes working during the positive and negative half‐cycles of the utility voltage, respectively, thus preventing the output current from flowing through the body diodes of switches. Because of its natural configuration, simple operation, and three‐level function, the proposed topology features a high level of efficiency and reliability over a wide voltage range, and allows the best cost–effective ratio. These characteristics are compared with those of other existing advanced topologies, followed by a theoretical analysis on the output filter and the implemented circuit of modulation scheme. Experimental results from a 3 kW hardware prototype verify the feasibility of the proposed solution. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A low‐power technique for high‐resolution dynamic comparators

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (V_cm) range of 0‐Vdd/2.     

A battery charger with maximum power point tracking function for low‐power photovoltaic system applications

A battery charger with MPPT function for low‐power PV system applications is presented in this study. For effective miniaturization, the battery charger is designed with high‐frequency operation. Some current‐sensing techniques are studied, and their MPPT implementation is compared. A battery charging method is also designed to prolong battery lifetime without the use of battery current sensors. The operation principles and design considerations of the proposed PV charger are analyzed and discussed in detail. A laboratory prototype is implemented and tested to verify the feasibility of the proposed scheme. Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high‐frequency operation. Copyright © 2010 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

Quasi‐active power factor correction on flyback‐based dc/dc converter

This paper presents a novel input current shaper based on a quasi‐active power factor correction (PFC) scheme. In this method, high power factor and low harmonic content are achieved by providing an auxiliary PFC circuit with a driving voltage which is derived from a third winding of the transformer of a cascaded dc/dc flyback converter. It eliminates the use of active switch and control circuit for PFC. The auxiliary winding provides a controlled voltage‐boost function for bulk capacitor without inducing a dead angle in the line current. Since the dc/dc converter operates at high switching frequency, the driving voltage is also of high switching frequency, which results in reducing the size of the magnetic components. Operating principles, analysis and experimental results of the proposed method are presented. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A low‐loss high‐power single‐pole 8‐throw antenna switch adopting body self‐adapting bias technique in a 0.18‐μm thick‐film partially depleted silicon‐on‐insulator complementary metal‐oxide‐semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body‐contacted field‐effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body‐contacted field‐effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self‐adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon‐on‐insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1‐dB compression point (P_?0.1dB), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P_?0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.     

A maximum power point tracking control method suitable for compact wind power generators with the passive self‐pitch‐controlled blade structure

This paper describes a maximum power point tracking (MPPT) control method for propeller‐type compact wind power generators with passive self‐pitch‐controlled blades, which quickly makes the output current and voltage converge on the maximum power point based on wind speeds detected from an anemometer. The voltage and current output from these wind power generators vary with wind speeds at locations such as the roofs of buildings. Transient characteristics of the voltage output from compact wind power generators have two modes because of the self‐pitch‐controlled blades: mode I in which the output voltage hardly increases and mode II in which it rapidly increases. Thus, in order to acquire the generated power effectively, irrespective of how the wind speeds may change, a method to perform the MPPT control while searching for mode II is needed. Thus, by judging the mode from the change of the sign of the time differential of the voltage deviation between sampling times, the MPPT control method proposed here makes the output current converge on the maximum point using relationships between the maximum power and optimal current which give the maximum power and the wind speed. Effectiveness of the proposed MPPT control method is verified through simulations and experiments using a wind tunnel. IEEJ Trans 2010 DOI: 10.1002/tee.20609     

A New PV Converter for Grid Connection Through a High‐Leg Delta Transformer Using Cooperative Control of Boost Converters and Inverters

This paper proposes a new high‐efficiency photovoltaic (PV) converter for grid connection through a high‐leg delta transformer, which is composed of a symmetrically connected boost converter and three half‐bridge inverters. One of the three half‐bridge inverters is connected to the boost converter, and the others are directly connected to the PV terminals. This circuit configuration enables to reduce the power losses in both boost converter and inverter. This paper also proposes a new cooperative control method between the symmetrically connected boost converter and inverter. The control method can reduce the average switching frequency to 75% of that in a conventional one, resulting in a great reduction in switching power loss. Experimental results show that the proposed circuit improves its European efficiency from 91.6% to 94.5%.     

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

Effects of output power fluctuation on short‐circuit current of induction‐type wind power generators

Effects of the fluctuation inherent in wind speed are studied by a probabilistic method. The random variation in wind speed is responsible for random behavior in output power and internal voltage of a wind power generator. In case of fault occurrence at the instant of high internal voltage, the resultant short‐circuit current will be big, and vice versa. The DC component is also affected. According to the study, 2.4% and 1.3% increase of short‐circuit current in AC and DC components are observed respectively in a large variation case. This implies that the wind speed variation should be considered for accurate short‐circuit study. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(3): 27–36, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20721     

Reactive Power Control of Mega‐Solar System for Voltage Regulation with Long Distribution Line

Constant power factor control of a power conditioning system in a large‐scale photovoltaic generation system (PV system) such as a mega‐solar system is introduced to mitigate voltage variations on a distribution line. However, it is difficult for the control to mitigate the voltage variation on a long distribution line because of the changes in the loss on the distribution line. This paper proposes an advanced reactive power control in which the power factor of the PV system is adjusted using both the output power of the PV system and the apparent power of loads not to minimize the voltage variation at the interconnecting point but to minimize the voltage variation over the whole distribution line. We report on the results based on numerical analysis on mitigating the voltage variation by applying this control. This paper shows that the proposed control can mitigate the voltage variation better than constant power factor control can. The proposed control has the potential to be used as a measure for suppressing voltage variations on a long distribution line.     

A novel multi‐output high‐voltage‐isolated power supply system for semiconductor device series‐connected switches

This paper presents a novel scheme of a multi‐output power supply for solid‐state switches based on series‐connected semiconductor devices. By using the loosely transforming method, the system can realize high‐voltage isolation and a compact size, and its application range can be easily expanded to modular designed switch stacks for higher power ratings. The circuit structure and working principles are described. Based on the system operating equations, the design methodology is proposed and applied for parameter specification of a power supply system of two series‐connected switch stacks containing 20 outputs. Detailed calculations are given, and experimental results prove the feasibility of the proposed scheme. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

Analysis and implementation of a high step‐up converter for fuel cell power‐generation systems

This paper presents a high step‐up converter, which utilizes a three‐winding coupled inductor and a rectified voltage‐doubler circuit to obtain high step‐up gain for fuel cells. The proposed converter functions as an active‐clamp circuit, which relieves large voltage spikes across the power switches. Thus, power switches with low‐voltage‐rated can be utilized to reduce conduction losses and circuit cost. Energy stored in leakage inductances of the coupled inductor is recycled to the output terminal, resulting in efficiency improvements. In addition, the coupled inductor in the presented converter can also have extra windings in order to achieve higher voltage gain. Finally, a prototype circuit with an input voltage of 60 V and an output voltage of 380 V is developed for a 1000 W‐rated fuel cell power‐generation system to validate its performance, and experimental waveforms and measured efficiency under different input voltages and output power level are demonstrated. Copyright © 2016 John Wiley & Sons, Ltd.     

New SRAM design using body bias technique for low‐power and high‐speed applications

In this paper, a new SRAM cell with body‐bias actively controlled by a control circuit and word line is introduced to realize low‐power and high‐speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade‐off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.