超宽带高速卷积译码器设计与实现

超宽带系统卷积译码器在芯片实现中面临高速率、低功耗的挑战,本文在分析比较了多种Viterbi译码算法和结构的基础上,提出了一种适合芯片实现的并行回溯的译码器结构。该结构通过牺牲30%的存储资源以增加并行回溯分支,从而译码器工作时钟降至传统结构的一半。仿真和测试表明,该译码器在没有损失性能的情况下,单个译码模块速率可达到220Mbps,延时只有2.4μS,可支持低延时的突发模式。     

Theoretical analysis of concurrent flashover characteristics in a three‐parallel gap configuration

Concurrent flashover characteristics with three gaps in parallel are analyzed theoretically considering the statistical characteristics of time to flashover of a gap. The analysis shows that the concurrent flashover phenomena are likely to occur if the overvoltage ratio is large even if there are three gaps. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Implementation of parallel zero‐voltage switching converter with series‐connected transformers

This paper presents a parallel zero‐voltage switching (ZVS) DC–DC converter with series‐connected transformers. In order to increase output power, two transformers connected in series are used in the proposed converter. Two buck‐type converters connected in parallel have the same switching devices. The primary windings of series‐connected transformers can achieve the balanced secondary winding currents. The current doubler rectifiers with ripple current cancellation are connected in parallel at the output side to reduce the current stress of the secondary winding. Thus, the current ripple on the output capacitor is reduced, and the size of the output choke and output capacitor are reduced. Only two switches are used in the proposed circuit instead of four switches in the conventional parallel ZVS converter to achieve ZVS and output current sharing. Therefore, the proposed converter has less power switches. The ZVS turn‐on is implemented during the commutation stage of two complementary switches such that the switching losses and thermal stresses on the semiconductors are reduced. Experimental results for a 528‐W (48 V/11 A) prototype are presented to prove the theoretical analysis and circuit performance. Copyright © 2011 John Wiley & Sons, Ltd.     

基于FPDP和VME总线的多DSP通用并行处理系统设计

多信号处理板多处理器系统已经广泛应用于高速信号处理领域。多处理器的结构和子板间的数据传输速度是系统设计的难点。本文具体介绍一种双总线的高速信号处理多子板结构系统。基于VME总线的高可靠性以及FPDP总线的高速传输能力,系统采用VME总线完成板间程序下载,采用FPDP总线完成板间数据传输。并且提出一主三从的多处理器结构,增强了系统的重组性和扩展性。文中详细讨论了该系统中多DSP通用并行处理机的硬件设计,并就系统结构和供电方案给出原理框图。     

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

This paper presents secure data processing with a massive‐parallel single‐instruction multiple‐data (SIMD) matrix for embedded system‐on‐chip (SoC) in digital‐convergence mobile devices. Recent mobile devices are required to use private‐information‐secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end‐user's operation for maintaining the safety condition. To satisfy these security‐related requirements, we propose the interleaved‐bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massive‐parallel SIMD matrix processor (MX‐1) for interleaved‐bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization‐approved block ciphers, a data encryption standard (DES), triple‐DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX‐1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX‐1 results are almost constant for all confidentiality modes. The practical‐use energy efficiency of parallel block cipher processing with the evaluation board for MX‐1 was found to be about 4.8 times higher than that of a BeagleBoard‐xM, which is a single‐board computer and uses the ARM Cortex‐A8 mobile processor. Furthermore, to improve the operation of a single‐bit logical function, we propose the development of a multi‐bit logical library for interleaved‐bitslice cipher processing with MX‐1. Thus, the number of clock cycles is the smallest among those reported in other related‐studies. Consequently, interleaved‐bitslice block cipher processing with five confidentiality modes on MX‐1 is effective for the implementation of parallel block cipher processing for several digital‐convergence mobile devices. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

大尺寸部件测量信息高速并行处理系统设计

针对航空、航天等工业中的大尺寸部件,传统的测量方法精度低、效率低,研发一种全视角、高精度的三维测量设备尤为必要。全视角图像信息处理是整个设备的关键,为了高速、高实时性地处理大尺寸图像信息,对高速并行图像处理技术进行研究,设计基于FPGA+双多核DSP的并行图像处理方案,实现系统硬件电路,提出并行处理的软件实现方法,将图像处理算法向硬件系统移植,对系统进行试验验证。对8 000×10 000的图像处理结果表明,单帧图像处理平均速度不大于0.15 s。     

A forward‐only recursion algorithm for MAP decoding of linear block codes

The evolution of digital mobile communications along with the increase of integrated circuit complexity has resulted in frequent use of error control coding to protect information against transmission errors. Soft decision decoding offers better error performance compared to hard decision decoding but on the expense of decoding complexity. The maximum a posteriori (MAP) decoder is a decoding algorithm which processes soft information and aims at minimizing bit error probability. In this paper, a matrix approach is presented which analytically describes MAP decoding of linear block codes in an original domain and a corresponding spectral domain. The trellis‐based decoding approach belongs to the class of forward‐only recursion algorithms. It is applicable to high rate block codes with a moderate number of parity bits and allows a simple implementation in the spectral domain in terms of storage requirements and computational complexity. Especially, the required storage space can be significantly reduced compared to conventional BCJR‐based decoding algorithms. Copyright © 2002 John Wiley & Sons, Ltd.     

Efficient three‐dimensional parallel simulations of PHEMTs

An efficient 3D semiconductor device simulator is presented for a memory distributed multiprocessor environment using the drift–diffusion (D–D) approach for carrier transport. The current continuity equation and the Poisson equation, required to be solved iteratively in the D–D approach, are discretized using a finite element method (FEM) on an unstructured tetrahedral mesh. Parallel algorithms are employed to speed up the solution. The simulator has been applied to study a pseudomorphic high electron mobility transistor (PHEMT). We have carried out a careful calibration against experimental I–V characteristics of the 120 nm PHEMT achieving an excellent agreement. A simplification of the device buffer, which effectively reduces the mesh size, is investigated in order to speed up the simulations. The 3D device FEM simulator has achieved almost a linear parallel scalability for up to eight processors. Copyright © 2005 John Wiley & Sons, Ltd.     

Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm² the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.     

平行集束电缆的制造及新型模具设计

本文就平行集束电缆生产中常见的质量问题提出了相应的措施 ,还设计了一种新型挤出模具 ,可较好的解决绝缘偏心问题     

Technologies and applications of Al‐free high‐power laser diodes

We report high‐power technologies in 0.8‐µm Al‐free InGaAsP/InGaP laser diodes. To realize the high‐power operation, the improvement of catastrophic optical mirror damage (COMD) power density level is required. In addition to the use of low surface recombination velocity of Al‐free materials, optimization of waveguide thickness in broad waveguide structure with tensile‐strained barriers and current blocking structure near facets has led to high COMD power density level. Highly stable operation of Al‐free laser diodes with these structures has been obtained over 2500 hours at 2 W from a stripe width of µm. Applications of high‐power laser diodes are also described. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 158(1): 53–59, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20286     

A study of series‐parallel changeover circuit of a capacitor bank for an energy storage system utilizing electric double‐layer capacitors

Electric double‐layer capacitors showing a remarkably high energy density (compared with conventional electrolytic capacitors) are now under development. Capacitors of this type have significant advantages, namely, high durability against repeated charge and discharge and no need for maintenance. Therefore, we have studied feasible basic circuit configurations and control methods required to apply electric double‐layer capacitors as an energy storage element in output‐power leveling systems for solar cells or windmill power generators, and in uninterruptible power supply systems. This paper discussed operating methods for a capacitor bank to improve the efficiency. High efficiency has been demonstrated by the simulations and the experiments. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(3): 33–42, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10155     

一种交错并联零电流软开关双向DC/DC变换器设计*

针对传统交错并联式双向DC/DC变换器在高频大功率工作时,开关管损耗大的问题,设计了一种零电流软开关交错并联式双向DC/DC变换器;通过在开关过程前后引入谐振,实现零电流开通和零电流关断,降低开关损耗;进一步分时段模态分析了Boost/Buck模式下的电路工作机理,并在其基础上提出了一种适用于特定占空比的改进型零电流软开关双向DC/DC变换器。最后,通过仿真对比,验证了所设计零电流软开关变换器能量转换效率得到了提高。     

Synthesis and application of a real‐time model‐free behavioral controller with bumpless switching mechanism

The aims of this paper are twofold. Firstly, we present a model‐free algorithm for synthesizing an online controller. Secondly, this algorithm also addresses the issue of switching this controller in a closed loop with a bumpless interconnection mechanism. The novelty of this algorithm lies in the fact that we do not use any a priori knowledge of the model of the plant in real time. We use the mathematical framework of behavioral system theory to demonstrate the online controller synthesis and its implementation mechanism. The effectiveness of the proposed algorithm is demonstrated on the experimental three‐tank system. Copyright © 2015 John Wiley & Sons, Ltd.     

Parallel processing of steady‐state analysis for a power electronic system by PVM3

It is important to get a steady‐state operation of a power electronic circuit for its design. The shooting method, which is one of the steady‐state analysis methods, solves a boundary value condition which equates initial values to final values after one‐period transient. This paper proposes how to process the analysis in parallel by using a Parallel Virtual Machine (PVM3) system. In particular, the multiple shooting method (MSM) which divides the shooting time into subsections is suitable because it can parallel numerical processes for the divided shooting times by using multiple CPU units independently. This parallel method is applied to converter examples which are processes by PVM3. The computed results are investigated for their convergence and CPU times to check their parallel effects. According to the MSM algorithm, CPU times are reduced almost to one‐fifth by using five computer units from a PVM3 system example. © 2001 Scripta Technica, Electr Eng Jpn, 135(2): 69–76, 2001     

Application of parallel tabu search‐based hierarchical optimization to distribution system service restoration

This paper proposes a hybrid method of hierarchical optimization and parallel tabu search (PTS) for distribution system service restoration with distributed generators. The objective is to evaluate the optimal route to recover the service. The improvement of power quality makes the service restoration more important. Distribution system service restoration is one of the complicated combinational optimization problems that are expressed as nonlinear mixed integer programming. In this paper, an efficient method is proposed to restore the service in a hierarchical optimization with PTS. The proposed method is tested in a sample system. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 164(4): 15–23, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/ eej.20463     

A force‐reflecting friction‐free bilateral system based on a twin drive control system with torsional vibration suppression

This paper proposes a new friction‐free bilateral system based on twin drive control system considering resonant frequency for bilateral systems. The twin drive system consists of two motors which are coupled by the differential gear. The output torque becomes a different torque of both motors. The nonlinear friction torque of the twin drive system can be easily compensated. However, the resonant frequency and the antiresonant frequency caused by the tensional vibration exist. This paper proposes a new two‐mass model of twin drive system that supresses torsional vibration by state feedback. The proposed control method is applied to the bilateral robot, and the effectiveness of the control method is confirmed by the experimental results. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 159(1): 72–79, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20355     

Application of model‐free LQG subspace predictive control to TCP congestion control

We investigate the application of a model‐free linear quadratic Gaussian (LQG) subspace‐based predictive controller to Internet congestion control. Specifically, we consider a classically designed LQG linear congestion controller with a non‐standard performance index and determine whether a model‐free controller is a viable alternative in this instance. We employ the model‐free subspace predictive controller methodology which we customize for end‐to‐end transmission control protocol (TCP) congestion control. A series of network simulations support the use of the more easily implementable model‐free controller over its classical analogue. We further demonstrate that the model‐free controller provides increased stability under transient network conditions when compared with the first feedback congestion controller, TCP Vegas. Copyright © 2007 John Wiley & Sons, Ltd.     

A feasibility study of a direct-mapping parallel processing method to solve linear equations in load-flow calculation

With the growing size and complexity of power systems, system analysis—such as transients calculation—takes much time. Hence, fast calculation methods are required. Although parallel processing is a hopeful method, there have been difficulties in the parallel solution of linear equations which appear in power-flow calculations by the Newton-Raphson method. This paper aims at the fast calculation of the power-flow problem by means of parallel processing. In order to improve the suitability to the parallel solution of the differential equation in transients calculation, we assume the use of a direct-mapping parallel processing machine to map directly the network of a power system onto a network of processors. Under this assumption, we propose a new parallel-processing-oriented method in which the linear equation is solved by linear iterations between nodes with Aitken acceleration. We simulate the method on three model power systems and compare this Parallel Iterative Method (PIN) with a Parallel Direct Method (PDM) which uses the banded matrix according to the number of operations required. As a result, we can expect that PIM may solve linear equations faster than PDM with m processors, although the PIM might be inferior to the PDM with m × m processors, where m denotes the half-band width of the banded matrix.     

Optimal model‐free control for a generic MIMO nonlinear system with application to autonomous mobile robots

In this paper, the design procedure for optimal model‐free control algorithm is presented for the tracking problem of completely unknown nonlinear dynamic systems operating under unknown disturbances. The procedure includes a new structure in the context of model‐free control and data‐driven control algorithms. In the new structure, the unknown nonlinear functions are segmented into 1 unknown linear‐in‐states part and another unknown nonlinear part. The adaptive laws proposed for estimating the unknown system dynamics are regressor‐free estimation methods in which there is no need for regressor parameters and, consequently, the persistent excitation condition is not required anymore. Moreover, the main controller gains are updated online, incorporating the adapted values of linear terms in the system dynamics. A comparative study is presented to show that the proposed optimal model‐free control outperforms the state‐of‐the‐art model‐free control algorithms. In addition, the simulation results for the application of the algorithm on autonomous mobile robots are provided.