共查询到20条相似文献,搜索用时 15 毫秒
1.
设计和实现超高速快速傅里叶变换器(FFT)在雷达与未来无线通信等系统中具有重要意义。该文提出首个全并行架构的FFT处理器,其避免了复杂的路由寻址以及数据访问冲突等问题,基于较大基进行分解降低运算复杂度。由于旋转因子已知和固定,大量的乘法转化为了定系数乘法。同时由于采用了串行的计算单元,在达到全并行结构的高速度同时硬件复杂度相对较低;所有的硬件计算单元处于满载的条件,其硬件效率能达到100%。根据实际的实现结果,所提出的512点FFT处理器结构能够达到5.97倍速度面积比的提升,同时硬件开销仅占用了Xilinx V7-980t FPGA 30%的查找表资源与9%的寄存器资源。 相似文献
2.
3.
Real-valued Fast Fourier Transform (FFT) plays an important role in today’s digital world because of the fact that most of the signals contain real values. The FFT computation of real signals using conventional techniques requires more hardware space with high power consumption, which is the most important task for a researcher while designing VLSI architectures. This can be eradicated by clearly analysing the symmetric property of the real-valued signals. In this paper, we have adopted the symmetric property and designed an efficient pipelined architecture for 16-point DIF FFT. The pipeline scheme reduce the processing time at the cost of some registers and in order to contribute efficiently for power reduction we have modified the complex multiplier with reduced internal real multipliers which are in turn replaced by an modified canonic signed digit multiplier (CSDM) with resource-sharing technique. The complete module is synthesised and simulated using Xilinx ISE 14.1 with the target device is Virtex-5 xc5vlx110T. The experimental results verify that our implemented design is more efficient in terms of speed, area and power when comparing with similar works. 相似文献
4.
在用电设备中广泛使用各种电力电子器件,往往会引起供电电网电压波形发生畸变,即谐波污染,会带来许多危害。在线电网谐波分析仪就是为了监测电力谐波污染而设计的。其整个设计过程采用模块化设计的思想。系统硬件主要包括电源模块,传感器前端电路模块,TMS320F2812数字信号处理器(DSP)主电路板模块。系统软件主要包括人机界面(HMI)程序模块,模数转换(ADC)程序模块,快速傅立叶变换(FFT)程序模块。 相似文献
5.
提出了一套快速傅里叶变换深能级瞬态谱(FFT-DLTS)测试系统,分析了该系统的硬件构成和软件流程,并给出了一个实例分析。最后,将FFT-DLTS与常规DLTS作了对比。 相似文献
6.
7.
8.
针对视觉跟踪中目标表观变化、局部遮挡、背景干扰等问题,该文提出一种基于快速傅里叶变换的局部分块视觉跟踪算法。通过建立目标分块核岭回归模型并构建循环结构矩阵进行分块穷搜索来提高跟踪精度,利用快速傅里叶变换将时域运算变换到频域运算提高跟踪效率。首先,在包含目标的初始跟踪区域建立目标分块核岭回归模型;然后,提出通过构造循环结构矩阵进行分块穷搜索,并构建目标分块在相邻帧位置关系模型;最后,利用位置关系模型精确估计目标位置并进行分块模型更新。实验结果表明,该文算法不仅对目标表观变化、局部遮挡以及背景干扰等问题的适应能力有所增强,而且跟踪实时性较好。 相似文献
9.
10.
本文深入探讨了FFT算法的特点,并对FFT算法在DSP上的实现方法进行了详细的分析.通过分析阐述并总结了利用DSP实现FFT算法的步骤及规律. 相似文献
11.
12.
13.
14.
沿航向的非匀速运动对SAR成像质量有很大影响,而运动补偿后SAR图像存在几何形变,影响子图像拼接和多波段SAR图像融合。当沿航向速度误差较大时,实图像域插值校正后图像残留的几何形变不能忽略。基于上述问题,该文提出一种基于非均匀傅里叶变换的SAR方位向运动补偿算法,算法直接对方位向的非均匀数据进行非均匀快速傅里叶变换(NUFFT)。该算法的定位误差和几何形变比实图像域插值校正几何形变算法小1到2个数量级,对沿航向速度误差有很强的鲁棒性,补偿后数据的幅度和相位信息都得以保留。SAR仿真和实测数据验证了该算法的有效性。 相似文献
15.
16.
In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-22 and radix-23 pipelined FFT architectures are modeled and implemented using TSMC 180 nm CMOS technology with a supply voltage of 1.8 V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures. 相似文献
17.
快速傅里叶变换(FFT)是离散傅里叶变换(DFT)的快速算法,广泛运用于故障诊断领域,因每种故障的频率成分不同,FFT可以根据这些独有的频率成分检测出不同的故障来。同时快速傅里叶变换还应用于控制工程、图像处理、机床生产、数据采集和雷达探测等方面,对社会中的工业发展起到很大的作用。本文就FFT对信号的频谱做出简单分析,对不同采样点数进行相应频谱判断,找出理论与频率图像出现误差的原因,以便人们对FFT技术能够进行更好的使用。 相似文献
18.
针对大规模的离散傅里叶变换(DFT)调制滤波器组设计算法复杂度高的问题,该文提出一种基于无约束优化的快速设计算法。该算法将两个原型滤波器的设计问题归结为一个无约束优化问题,将滤波器组的传递失真,混叠失真以及原型滤波器阻带能量的加权和作为目标函数。进而,采用双迭代机制来求解该优化问题。在单步迭代中,运用矩阵求逆的等效条件和Toeplitz矩阵求逆的快速算法,显著地降低了迭代的计算代价。仿真对比表明,与已有的设计算法相比,新算法计算代价低 ,可以得到整体性能更好的滤波器组,并且可以快速设计大规模的滤波器组。 相似文献
19.
高吞吐浮点可灵活重构的快速傅里叶变换(FFT)处理器可满足尖端雷达实时成像和高精度科学计算等多种应用需求。与定点FFT相比,浮点运算复杂度更高,使得浮点型FFT的运算吞吐率与其实现面积、功耗之间的矛盾问题尤为突出。鉴于此,为降低运算复杂度,首先将大点数FFT分解成若干个小点数基2k 级联子级实现,提出分别针对128/256/512/1024/2048点FFT的优化混合基算法。同时,结合所提出同时支持单通道单精度和双通道半精度两种浮点模式的新型融合加减与点乘运算单元,首次提出一款高吞吐率双模浮点可变点FFT处理器结构,并在28 nm标准CMOS工艺下进行设计并实现。实验结果表明,单通道单精度和双通道半精度浮点两种模式下的运算吞吐率和输出平均信号量化噪声比分别为3.478 GSample/s, 135 dB和6.957 GSample/s, 60 dB。归一化吞吐率面积比相比于现有其他浮点FFT实现可提高约12倍。 相似文献
20.
The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the Fast Fourier Transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM.We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to CLNS. We observe that CLNS saves 9–12 bits in word-size for 256–1024 point FFTs compared to the fixed-point number system while producing comparable accuracy.The consequence of the word-size advantage is that the number of full adders required for CLNS is significantly smaller than for an equivalent fixed-point implementation. The major cost of CLNS is the memory, which unlike conventional LNS, is addressed by both real and imaginary parts. Table-reduction techniques can mitigate this. The simplicity of the CLNS approach requires significantly fewer full adders, which pays for some or all of the extra memory. In applications needing the magnitude of the complex parts, such as a power spectrum, the CLNS approach can actually require less memory than the conventional approach. 相似文献