An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm² custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07 V supply.     

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-V_t) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.     

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.     

Millimeter-Wave Integrated Circuits in 65-nm CMOS

We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at $+$6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 ${hbox{mm}}^{2}$. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of $+$7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and $+$5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with $-$19 dBm of 1-dB output compression point.      

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.      

A Leakage-Compensated PLL in 65-nm CMOS Technology

A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14 mm².     

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

This paper presents an SEU-resilient 12 T SRAM bitcell. Simulation results demonstrate that it has higher critical charge than the traditional 6 T cell. Alpha and proton testing results validate that it has a lower soft error rate compared to the reference designs for all data patterns and supply voltage levels. The improvement in SEU tolerance is achieved at the expense of 2X area penalty.     

Sub-50-nm physical gate length CMOS technology and beyond usingsteep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with T_ox^inv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions     

Sub-1V CMOS Voltage Reference Based on Weighted Vgs

提出了一种新型CMOS恒压源的制作方案,它基于nMOS和pMOS的饱和区栅源电压随温度变化权重不同的原理,将两者做相关运算,得到零温度系数的恒压源.该电压源没有采用二极管和寄生三极管,并用SMIC 0.18μm数模混合工艺模型参数仿真并制造.测试结果表明,温度系数达到了44ppm/℃,PSRR为-46dB,650mV以上的电源电压就可以完全正常工作.芯片面积约为0.05mm2.     

A universal low-noise analog receiver baseband in 65-nm CMOS

In this paper, a novel universal receiver baseband approach is introduced. The chain includes a post-mixer noise shaping blocker pre-filter, a programmable-gain post mixer amplifier (PMA) with blocker suppression, a differential ramp-based novel linear-in-dB variable gain amplifier and a Sallen–Key output buffer. The 1.2-V chain is implemented in a 65-nm CMOS process, occupying a die area of 0.45 mm². The total power consumption of the baseband chain is 11.5 mW. The device can be tuned across a bandwidth of 700-KHz to 5.2-MHz with 20 kHz resolution and is tested for two distinct mobile-TV applications; integrated services digital broadcasting-terrestrial ISDB-T (3-segment f _c = 700 kHz) and digital video broadcasting-terrestrial/handheld (DVB-T/H f _c = 3.8 MHz). The measured IIP3 of the whole chain for the adjacent blocker channel is 24.2 and 24 dBm for the ISDB-T and DVB-T/H modes, respectively. The measured input-referred noise density is 10.5 nV/sqrtHz in DVB-T/H mode and 14.5 nV/sqrtHz in ISDB-T mode.     

Manufacturable Parasitic-Aware Circuit-Level FETs in 65-nm SOI CMOS Technology

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency f_T of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum f_T of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at sub-threshold voltages compatible with the logic. Since sub-threshold voltages leave less room for large static noise margin (SNM), a thorough understanding of the impact of various design decisions and other parameters becomes critical. This paper analyzes SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, V/sub DD/, temperature, and local and global threshold variation. The V/sub T/ variation has the greatest impact on SNM, so we provide a model that allows estimation of the SNM along the worst-case tail of the distribution.     

Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper

In this paper, efficient clock delayed domino logic with variable strength voltage keeper is proposed. The variable strength of the keeper is achieved through applying two different body biases to the keeper. The circuits used to generate the body biases are called capacitive body bias generator and cross-coupled capacitive body bias generator. Compared to a previous work, the body bias generator circuits presented in this paper are simpler and do not require double or triple power supply while consuming less area and power. To show the efficiency of the proposed technique, the implementation of a carry generator circuit by the proposed techniques and the previous work are compared. The simulation results for standard CMOS technologies of 0.18 mum and 70 nm show considerable improvements in terms of power and power delay product. In addition, the proposed technique shows much less temperature dependence when compared to that of previous work     

New Test Structure to Monitor Contact-to-Poly Leakage in Sub-90 nm CMOS Technologies

The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-of-the-art CMOS process technology.      

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as \(-\)21.4 dBm \((7.24\,\upmu \hbox {W})\). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from \(-40\hbox { to }125\,^{\circ }\hbox {C}\) which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.     

一种用于A/D转换器的低电压CMOS带隙电压基准源

设计了一种在1V电压下正常工作的用于A/D转换器的低功耗高精度的CMOS带隙电压基准.电路主要包括了一个带隙基准和一个运放电路,而且软启动电路不消耗静态电流.电路采用0.18μm CMOS工艺设计.仿真结果显示,温度从-40~125°C,温度系数约为1.93ppm/°C,同时电源抑制比在10kHz时为38.18dB.电源电压从0.9V到3.4V变化时,输出电压波动保持在0.17%以内;电路消耗总电流为5.18μA.     

65-nm CMOS Voltage-to-Time Converter for 5-GS/s Time-Based ADCs

This paper discusses a voltage-to-time converter (VTC) designed for use in a time-based analog-to-digital converter. The VTC considered in this work is based on a starved-inverter topology. Linearity, delay, and jitter of the VTC are analyzed to facilitate a physical understanding of the circuit performance. The design is experimentally verified in a 65-nm CMOS technology. Measurement results show that the VTC, operating with a 5-GHz clock, has an output delay range of \(\pm 25\,{\text{ ps }}\), 4.4 effective number of bits (ENOB), and output jitter of \(0.5\,\text{ ps }\) RMS while consuming 4 mW of power. The input effective resolution bandwidth (ERBW) of the VTC is measured to be 4.1 GHz, over which the ENOB remains above 3.5 bits. The same VTC, operating with a 7.5-GHz clock, consumes 9.7 mW of power from a 1.2-V supply, has ENOB of >3.8 bits, ERBW of >7 GHz, output jitter of \(0.4\,\text{ ps }\) RMS, and output delay range of \(\pm 25\,\text{ ps }\). The VTC achieves the widest input bandwidth of any VTC reported to date.