Yaffs2文件系统中对NAND Flash磨损均衡的改进

针对以NAND Flash为存储介质时Yaffs2文件系统存在磨损均衡的缺陷,通过改进回收块选择机制,并在数据更新中引入冷热数据分离策略,从而改善NAND Flash的磨损均衡性能.实验借助Qemu软件建立Linux嵌入式仿真平台,从总擦除次数、最大最小擦除次数差值和块擦除次数标准差等方面进行对比.实验结果表明,在改进后的Yaffs2文件系统下NAND Flash的磨损均衡效果有明显提升,这有益于延长NAND Flash的使用寿命.     

基于地址映射的NAND Flash控制器设计

针对嵌入式数据采集系统对NAND Flash进行读写控制时出现的坏块问题和磨损失衡问题,对数据采集系统的工作特点进行分析,借鉴闪存转换层的思想,提出了一种基于地址映射的NAND Flash控制方法,通过建立、维护、查询NAND Flash存储块逻辑地址与物理地址之间的映射关系表,实现NAND Flash的坏块管理和磨损均衡功能,同时介绍了使用地址映射方法的NAND Flash控制器设计过程;仿真测试和实际应用结果表明,基于地址映射方法设计的NAND Flash控制器能够识别、管理出厂坏块和突发坏块,均衡存储块的磨损,提高嵌入式数据采集系统的可靠性;该方法实现过程简单,无需移植文件系统,硬件资源要求低,为嵌入式数据采集系统中NAND Flash的读写控制提供了新的思路。     

YAFFS在嵌入式Linux系统中的构建与改进

针对目前YAFFS文件系统启动时间过长、磨损平衡性差的缺陷,在借助嵌入式平台Lin-ux-2.6.28+ARMS3C2440构建YAFFS的基础上改进文件系统,即在启动时采用空间换取时间策略,为文件属性节点分配专门的存储区,减少扫描区域,达到缩短加载时间的目的;在垃圾回收时采用擦除计数机制,根据计数器选择擦除块,从而改善擦除块间的磨损平衡。通过实验证明了改进策略的有效性。     

基于NAND Flash的CPU安全启动设计与实现

NAND Flash存储器以其容量大、成本低和速度快的优势,在嵌入式系统中得到广泛的应用。但是,由于NAND Flash固有的器件特性,必须要有驱动才能对其进行读写,存储于其上的代码不能直接执行,因此其并不适合作为系统启动代码的存储介质。一般采用NOR Flash存储启动代码并直接执行,然后再引导存储于NAND Flash中的操作系统镜像,这增大了系统成本和功耗。设计并实现了一种基于NAND Flash的CPU安全启动方法。该方法首先通过软硬件结合的方式,在片内NAND Flash控制器中增加块映射表结构,并由NAND Flash中第1块空间存储的代码进行好块寻找和块映射表填写,使NAND Flash的一部分存储空间可以直接映射为硬件可访问的内存空间,从而使得NAND Flash可以作为系统启动的存储介质,实现仅需NAND Flash存储的系统。还提出了一种扩展BootROM的方案,结合NAND Flash地址映射结构,将片内BootROM的一部分扩展到NAND Flash的第1块存储空间中,并通过Hash比对验证BootROM,从而有效降低了片内BootROM的设计复杂度,减少了代码量。通过提出的方法,可以有效地实现单NAND Flash系统的安全启动,降低了系统成本,提高了系统的安全特性。     

基于贪婪策略的NAND FLASH存储器的磨损均衡算法研究

NAND FLASH存储器是无线传感器网络节点的存储设备。传感器节点在监控区域中不断获取数据信息,并进行节点之间的数据交互,使得NAND FLASH存储器频繁地进行写操作,从而造成物理块的擦除次数不均衡,缩短了存储器的使用寿命,最终影响整个传感器网络的使用寿命。针对上述问题,提出了贪婪策略的分区地址映射磨损均衡算法。该算法根据磨损擦除的参数进行贪婪选择,选择出擦除次数小的物理块进行写操作,而对擦除次数大的物理块进行配置与实验数据迁移,进入等待擦除。通过软件测试的方式,证明了所提算法可以有效地实现并优化NAND FLASH存储器的磨损均衡。     

基于USB2.0总线的NAND Flash检测及控制方法

在高速大容量存储装置设计中多采用NAND Flash存储器,针对目前采用串口检测坏块、实现数据读写的方法存在检测速度慢、等待时间长等缺点,提出了基于USB2.0总线的NAND Flash检测与控制方法。利用FPGA逻辑控制功能和高速USB接口芯片设计通信和控制电路,并通过上位机软件实现对Flash的命令、操作控制,由用户通过PC应用程序完成对NAND Flash的读写、擦除检测及坏块标定。经实验应用验证,该方法检测、读写速度快,使用灵活,能准确、有效实现数据的快速读写、擦除及坏块标定,可广泛应用于存储测试装置的设计研制中。     

大容量NAND Flash文件系统转换层优化设计

针对基于NAND Flash转换层(NFTL)架构的Flash文件系统在大容量NAND Flash设备上存在的性能不足,本文分析了NFTL的存储管理机制,基于vxworks嵌入式系统平台提出了对NFTL模块的优化设计方法并进行了具体实现。实验表明,优化后的NFTL模块有效提高了文件系统的读写性能,缩短了加载时间。     

基于STM32的NAND flash的块分配框架设计

STM32对大容量数据文件存储与管理问题可通过NAND flash来解决;而NAND flash的高效管理需要文件系统参与;NAND flash有特殊的块读写及擦除机制,一般的嵌入式文件系统组织结构并不完全兼容NAND flash;针对NAND flash的特点兼顾STM32的资源承受力要提出新的NAND flash块分配框架,框架通过块分配槽这种数据结构,在不使用块分配表与垃圾表的情况下,实现了NAND flash均衡负载与垃圾块的回收;同时通过节点分配栈与文件节点表的结合来提高STM32对文件的读写速度,空间利用率和系统性能;仿真实验和计算结果表明该块分配框架可有效提高NAND flash块的均衡负载与节省RAM空间.     

基于权重堆排序的NAND Flash静态磨损均衡机制

磨损均衡机制作为闪存转换层的基础机制之一,其主要功能是延长闪存块使用寿命和提高存储数据的可靠性。现有的磨损均衡机制着重于减少闪存块的擦除次数,忽略了在磨损均衡操作过程中选择擦除脏块的不合理所带来的不必要数据迁移开销,从而影响了固态硬盘的整体读写性能。针对该问题,提出了一种基于权重堆排序的 NAND Flash静态磨损均衡机制WHWL。首先,提出一种基于页数据访问频率和块擦除次数的权重的热度计算方法,有效地提高擦除次数少（冷块）且数据访问频率低（冷数据）的目标块命中率,避免了多余的数据迁移操作;其次,提出了一种基于权重的堆排序目标块选择算法,以加快目标块的筛选。实验结果表明,与现有的PWL和BET算法相比,在使用相同映射机制的条件下,WHWL能够分别提升固态硬盘寿命1.28、5.83倍,数据迁移次数也有明显的降低。     

基于NAND Flash启动的U-Boot设计与实现

介绍了S3C2410微处理器与NAND Flash的接口电路,分析了从NAND Flash启动的引导加载程序U-Boot的设计思路,并重点阐述了从NAND Flash启动的程序设计,重新编写了U-Boot的重定位代码,实现了U-Boot从NAND Flash的启动.通过串口终端的打印信息证明U-Boot成功从NAND Flash中启动,整个嵌入式系统运行良好.     

Android存储系统中NAND闪存性能的改进

针对Android存储系统在闪存管理上存在较差的磨损均衡效果和较高的垃圾回收额外开销的缺陷,引入冷热数据分离策略,将文件按照不同热度写入对应热度的物理存储单元,同时改进垃圾回收策略,以达到良好的磨损均衡效果并减少垃圾回收额外开销。基于Android平台的实验结果表明,改进后的策略在有效减少NAND闪存垃圾回收额外开销的同时,还能有效改善其磨损均衡效果。     

嵌入式Linux下NAND存储系统的设计与实现

讨论嵌入式Linux下与NAND闪仔存储设备相关的Linux MTD子系统、NAND驱动，并就与NAND闪存相关的文件系统、内核以及NAND闪存存储没计所关注的问题如坏块处理、从NAND启动、当前2．4和2．6内核中NAND通用驱动所存在的缺陷进行讨论并给出解决方案。以Omap161x H2开发板为例，给出了NAND闪存存储实现实例并指出设计中需要关注的问题。     

基于逻辑区间热度的NAND闪存垃圾回收算法

针对现有的NAND闪存垃圾回收算法中回收性能不高,磨损均衡效果差,并且算法内存开销大的问题,提出了一种基于逻辑区间热度的垃圾回收算法。该算法重新定义了热度计算公式,把连续逻辑地址的NAND内存定义为一个热度区间,以逻辑区间的热度来代替逻辑页的热度,并将不同热度的数据分开存储到不同擦除次数的闪存块上,有效地实现了数据冷热分离,并且节约了内存空间。同时,算法还构造了一种新的回收代价函数来选择回收块,在考虑回收效率的同时,还兼顾了磨损均衡的问题。实验结果表明,该算法与性能优异的FaGC算法相比,总的擦除次数减少了11%,总的拷贝次数减少了13%,擦次数最大差值减少了42%,内存消耗能减少了75%。因此,该算法有利于增加闪存可用空间,改善闪存系统的读写性能,延长闪存使用寿命。     

基于逻辑页冷热分离的NAND闪存磨损均衡算法

针对现有的NAND闪存垃圾回收算法对磨损均衡考虑不足的问题,提出了一种基于逻辑页冷热分离的NAND闪存磨损均衡算法。算法同时考虑了无效页的年龄、物理块的擦除次数以及物理块更新的频率,采用混合模式选择回收符合条件的物理块。同时,推导了一种新的逻辑页热度计算方法,并将回收块上有效页数据按照逻辑页的热度进行了冷热分离。实验结果表明,与GR算法、CB算法、CAT算法以及FaGC算法相比,该算法不仅在磨损均衡上取得了很好的效果,而且总的擦除次数与拷贝次数也有了明显减少。     

闪存文件系统的快速挂载机制设计与实现

基于嵌入式文件系统CFFS提出一种快速挂载机制。该机制引入“静态超级块”、“引用节点”以及“页位图”等数据结构并采取相应算法,避免了在文件系统挂载过程中进行的全芯片扫描。测试表明,这种快速挂载机制减少了闪存文件系统在大容量NAND芯片上的挂载时间。     

A high performance NAND array file system based on multiple NAND flash memories

The existing NAND flash memory file systems have not taken into account multiple NAND flash memories for large-capacity storage. In addition, since large-capacity NAND flash memory is much more expensive than the same capacity hard disk drive, it is cost wise infeasible to build large-capacity flash drives. To resolve these problems, this paper suggests a new file system called NAFS for large-capacity storage with multiple small-capacity and low-cost NAND flash memories. It adopts a new cache policy, mount scheme, and garbage collection scheme in order to improve read and write performance, to reduce the mount time, and to improve the wear-leveling effectiveness. Our performance results show that NAFS is more suitable for large-capacity storage than conventional NAND file systems such as YAFFS2 and JFFS2 and a disk-based file system for Linux such as HDD-RAID5-EXT3 in terms of the read and write transfer rate using a double cache policy and the mount time using metadata stored on a separate partition. We also demonstrate that the wear-leveling effectiveness of NAFS can be improved by our adaptive garbage collection scheme.     

Real-time emulation and analysis of multiple NAND flash channels in solid-state storage device

NAND Flash is the most prevalent memory technology used today in data storage systems covering a wide range of applications, from consumer devices to high-end enterprise systems. In this work, we present a modular and versatile FPGA-based platform that achieves accurate emulation of multiple NAND Flash channels. The NAND Flash emulator is based on an expandable and reconfigurable architecture that can be used for developing and testing new NAND Flash controllers and for analysing the behaviour of existing NAND Flash controllers and/or host device drivers. The presented NAND Flash emulator is based on PCIe-based FPGA boards attached to a high-end server, supports standard memory interfaces, responds to all memory commands in proper time and has the capability to emulate memory space in the range of a few TBs. The NAND Flash emulator has been prototyped and tested, and experimental results demonstrate that all timing requirements are satisfied under maximum read/write workloads. The NAND Flash emulator also includes a hardware tracer unit that records information of all commands exchanged at the NAND Flash interfaces along with high resolution timestamps. The recorded information can be used to analyse higher level functions, like wear leveling and garbage collection, and combined with other software tools for analysing cognitive functions. Experimental results demonstrate the advantage of using this emulator for analysing how host device drivers implement wear leveling and garbage collection functions.     

基于闪存设备分区的新型虚拟EEPROM设备的设计与研究

针对当前嵌入式系统对于低成本迫切需求,研究并设计了一种基于闪存设备（NAND FLASH）的新型虚拟EEPROM（Virtual EEPROM）设备。该设备被虚拟为操作系统NAND设备分区使用,使用数据备份机制确保数据信息安全性。针对NAND只支持页面单元的编程操作,使用缓冲区日志更新的方法,高效地解决Virtual EEPROM字节编程问题。最后通过设计损益均衡层实现NAND存储块的统一管理,对坏块和寿命问题进行大幅优化。分析结果表明,Virtual EEPROM具备NAND快速编程特性,擦写寿命较EEPROM有很大优势。该设计架构具备很好的系统兼容性,可以扩展移植于多种嵌入式平台。     

A user-visible solid-state storage system with software-defined fusion methods for PCM and NAND flash

Existing SSD technology exploits the properties of NAND flash and leverages NAND flash with a controller running FTL algorithms to improve system performance. On one hand, however, in this black-box-modeled structure, data semantic information is hard to be transferred and interpreted by conventional interfaces. Hence, SSD firmware fails to make full use of the performance potential of SSD by utilizing semantic information. Moreover, the host cannot obtain physical characteristics and statistical information about SSD, failing to be used by the file system or I/O scheduling algorithm designed for the disks. On the other hand, in SSD-based storage systems, persistent data are stored in the NAND flash and however manipulated in DRAM, causing the decoupled inefficiency. The data being closer to the processors are much easier to be lost due to the volatile property of DRAM, leading to serious data reliability problems. What’s more, restrictive read/program granularity and out-of-place updates limit the performance while flash suffers from small size operations.In order to address these problems, we propose a user-visible solid-state storage system with software-defined fusion methods for PCM and NAND flash. PCM is used for improving data reliability and reducing the write amplification of NAND flash as PCM shows some outstanding features, such as in-place updates, byte-addressable, non-volatile properties and better endurance. In this system, we manage the storage device as user-visible structure rather than black-box-modeled structure. In detail, we expose the number of channels, erase counts and data distribution of PCM/NAND flash to the host and design FTL algorithm closer to file system to obtain more semantic information of data accessing. PCM can be software-defined as the same level storage or buffer of NAND flash to reduce the WA (Write Amplification) of NAND flash and improve the data reliability. Moreover, some key software components (such as FTL, I/O scheduling and buffer management) are also reconfigurable and operated easily combined with physical characteristics. To achieve these design goals, we implement a Host Fusion Storage Layer (HFSL) and redesign the lengthy I/O path. Applications or filesystem can access PCM/flash directly via provided interfaces by HFSL without passing traditional I/O subsystem. Moreover, we provide the system management software to make the storage system can be easily software-defined by the upper-level system. We implement our software-defined fusion storage system in our actual hardware prototype and extensive experimental results demonstrate the efficiency of the proposed schemes.