The effect of test system impedance on measurements of groundbounce in printed circuit boards

Based on the 3D-FDTD approach, an efficient equivalent model employing the embedded resistive voltage source is proposed to simulate the effect of test system impedance on the measurement of the ground bounce noise for the power planes structure in the printed circuit boards (PCB). Compared with the measured results by vector network analyzer, this equivalent model well predicts the impedance behavior of the V_cc/GND power planes. The influences of different probe loading conditions of the test system on the measurement of impedance behavior are studied. It is found that the effects of the probing loads on the measurement of the ground bounce noise is significant at the frequencies near the dc point and resonance, but the influences of the probes are small at the frequencies far from resonance. In addition, the transfer characteristics of the power bus in the realistic digital circuits with decoupling capacitance being considered are simulated in the FDTD model. The difference of the transfer behavior between the realistic case without coaxial feed and the measured results with probing effects is also numerically compared. We find that the ground bounce noise in the real circuit can be accurately measured at most frequencies, where the power planes act in very low impedance, except at the frequencies near dc and resonance frequencies, where the power planes behave in relatively higher impedance characteristics     

An electromagnetic crystal power substrate with efficient suppression of power/ground plane noise on high-speed circuits

An electromagnetic crystal power substrate (ECPS) in a high-speed circuit package is proposed for suppressing the power/ground planes noise (P/GPN) and the corresponding electromagnetic interference (EMI). The ECPS is simply realized by periodically embedding the high dielectric-constant rods into the conventional package substrate between the continuous power and ground planes. With a small number of embedded rods and low rod filling ratio, the proposed ECPS design can efficiently eliminate the noise of 30dB in average within several designed stopbands. In addition, the radiation or EMI resulting from the P/GPN is also significantly reduced over 25dB in the stopbands. The excellent noise and EMI suppression performance for the proposed structure are verified both experimentally and numerically. Reasonably good consistency is seen.     

EMI mitigation with multilayer power-bus stacks and via stitchingof reference planes

General methods for reducing printed circuit board (PCB) emissions over a broad band of high frequencies are necessary to meet EMI requirements, as processors become faster and more powerful. One mechanism by which EMI can be coupled off a PCB or multichip module (MCM) structure is from high-frequency fringing electric fields on the DC power and reference planes at the substrate periphery. An approach for EMI mitigation by stitching multiple ground planes together along the periphery of multilayer PCB power-bus stacks with closely spaced vias is reported and quantified in this paper. Power-bus noise induced EMI and coupling from the board edges is the major concern herein. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. Design curves and an empirical equation are extracted from a parametric study to summarize the variation of the radiated EMI as a function of layer thickness and stitch spacing     

A Novel Time-Domain Approach for Extracting Broadband Models of Power Delivery NetworksWith Resonance Effect

Resonance noise, or power/ground bounce noise, on the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to synthesize the broadband models of the power/ground planes with resonance effect. Using waveforms either from measurements by time-domain reflectrometry or simulations by the finite-difference time-domain method, the time-domain step response of the planes is characterized with a pole-residue representation obtained through the matrix pencil method. Lumped circuit equivalent circuit models are then synthesized through the pole-residue representations. The synthesized model can accurately predict the resonance behavior of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the currently available circuit simulator such as HSPICE for the consideration of power/ground bouncing noise in high-speed circuits. Three cases are tested to demonstrate the validity and broadband accuracy of the proposed approach.      

A novel power planes with low radiation and broadband suppression of ground bounce noise using photonic bandgap structures

A novel power/ground planes design for eliminating the ground bounce noise (GBN) in high-speed digital circuits is proposed by using low-period photonic bandgap (PBG) structure. Keeping solid for the ground plane and designing low-period PBG pattern on the power plane, the proposed structure omni-directionally behaves highly efficient suppression of GBN (over 50 dB) within broadband frequency range from 1 GHz to 4 GHz. Although the power plane has low-period perforation, the proposed structure still performs with relatively low radiation within the stopband compared with the solid power/ground planes. The low radiation and high suppression of the GBN for the proposed structure are checked both experimentally and numerically. Good consistency is seen.     

Electromagnetic interference (EMI) reduction from printed circuit boards (PCB) using electromagnetic bandgap structures

As digital circuits become faster and more powerful, direct radiation from the power bus of their printed circuit boards (PCB) becomes a major concern for electromagnetic compatibility engineers. In such multilayer PCBs, the power and ground planes act as radiating microstrip patch antennas, where radiation is caused by fringing electric fields at board edges. In this paper, we introduce an effective method for suppressing PCB radiation from their power bus over an ultrawide range of frequencies by using metallo-dielectric electromagnetic band-gap structures. More specifically, this study focuses on the suppression of radiation from parallel-plate bus structures in high-speed PCBs caused by switching noise, such as simultaneous switching noise, also known as Delta-I noise or ground bounce. This noise consists of unwanted voltage fluctuations on the power bus of a PCB due to resonance of the parallel-plate waveguiding system created by the power bus planes. The techniques introduced here are not limited to the suppression of switching noise and can be extended to any wave propagation between the plates of the power bus. Laboratory PCB prototypes were fabricated and tested revealing appreciable suppression of radiated noise over specific frequency bands of interest, thus, testifying to the effectiveness of this concept.     

A novel power plane with super-wideband elimination of ground bounce noise on high speed circuits

A novel L-bridged electromagnetic bandgap (EBG) power/ground planes is proposed with super-wideband suppression of the ground bounce noise (GBN) from 600Mz to 4.6GHz. The L-shaped bridge design on the EBG power plane not only broadens the stopband bandwidth, but also can increase the mutual coupling between the adjacent EBG cells by significantly decreasing the gap between the cells. It is found the small gap design can prevent from the severe degradation of the signal quality for the high-speed signal referring to the perforated EBG power plane. The excellent GBN suppression performance with keeping reasonably good signal integrity for the proposed structure is validated both experimentally and numerically. Good agreement is seen.     

Time-domain approach for synthesising SPICE-compatible models of power delivery networks of printed circuit board

Resonance noise, or power/ground bounce noise, between the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to extract the equivalent circuit models of power/ground planes by time-domain reflection and time-domain transmission waveforms. The extracted model can accurately predict the resonance behaviour of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the HSPICE simulator for the consideration of power/ground bouncing noise in high-speed circuits.     

过孔转换信号完整性分析的区域分解有限元法

提出了一种基于区域分解的二维有限元法分析多层印制电路板电源/地平面中过孔转换结构的信号完整性.过孔电流产生的电磁场呈三维结构,其中,一部分电磁波沿过孔轴向传输,另一部分电磁波在电源/地平面间沿径向传播.采用一虚拟柱面将求解区域分割为过孔区和电源/地平面区.将过孔区建模为以周向磁场为主分量的二维轴对称问题,而将电源/地平面区建为以垂直电场为主分量的二维模型.首先求解电源/地平面区的二维边值问题获得分割边界上节点的波阻抗,然后将该波阻抗代入过孔区模型中分割边界节点的边界条件,从而计算出过孔信号传输的S参数.所提方法通过模型缩减可实现对微细过孔结构信号完整性的精确快速计算,且采用全波电磁场分析软件对算法的有效性和准确性进行了验证.     

Multiple Slope Switching Waveform Approximation to Improve Conducted EMI Spectral Analysis of Power Converters

An improved and simplified electromagnetic interference (EMI) modeling method based on multiple slope approximation of device-switching transitions for EMI analysis of power converters is presented. The traditional noise source modeling method, which uses single slope for rise and fall transition, is studied, and the criteria for reasonable modeling in the frequency range is analyzed. The turn-on and turn-off dynamics are investigated by dividing the nonlinear transitions into several stages based on an insulated gate bipolar transistor (IGBT) behavior circuit model. Real device-switching voltage and current waveforms are approximated by piece-wise linear lines and modeled by multiple dv/dt and di/dt slopes. The predicted EMI spectra suggest that high-frequency EMI noise is modeled with an acceptable accuracy. The proposed method was verified experimentally for a dc-dc buck converter     

印刷电路板供电系磁性材料涂层的应用

印刷电路板（PCB）的电磁兼容问题,随着数字电路的工作频率越来越高而变得尤为重要。本文以印刷电路板中的电源接地层供电系构造为切入点,讨论与其相关的电磁兼容问题。在高频段,印刷电路板的电源和接地层构造相当于一个平行平板谐振器,对周围的电路产生电磁干扰（EMI）。基于全腔模模型,已经发展了用于高效准确计算供电系阻抗的快速算法。利用此算法,通过计算机仿真,结果表明PCB电源接地层导体内侧增加磁性材料涂层能够提高表面阻抗,进而减小端口输入阻抗的谐振峰并改善信号完整性。     

Effects on signal integrity and radiated emission by split reference plane on high-speed multilayer printed circuit boards

Power/ground partitioning has been used to supply multivoltage levels and to isolate power/ground noise in high-speed multilayer printed circuit boards. However, the partitioning of the power/ground plane breaks the current return path of the signal current through either the power plane or the ground plane, which causes undesired effects such as signal distortion, crosstalk, and radiation. To control and suppress these undesired effects, we should understand the electromagnetic mechanism associated with them. In this paper, the mechanism of the reflection and the transmission of the signal by the slotted power/ground plane is well understood through an analysis of measurements based on time-domain reflectometry. Considering the propagation of a slot wave through the slot line on the power/ground plane, we have successfully explained the changes of the transmitted and reflected waveforms. Furthermore, we have numerically and experimentally investigated the effects of the power/ground partitioning on the radiated emission in various structures. Finally, it is confirmed that the employment of a stitching capacitor on the power/ground slot suppresses the signal distortion and the radiated emission significantly. When the size and the location of the stitching capacitor are designed, there should be a compromise between the noise isolation and the guarantee of the return current path, with considering the resonance frequencies of planes by the capacitor.     

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.     

基于PEEC结合网络缩减算法和递归卷积分析高速MCM电路中同步开关噪声

本文提出了一种分析高速MCM电路系统中电源/接地板上同步开关噪声的高效方法,即基于PEEC结合块缩减算法和递归卷积公式.该方法具有参数提取简单、高效率、高精度特点.同时,还提出了一种分级建模方法,若已知小尺寸电源/接地板的时域宏模型,利用该方法可在时域直接分析大尺寸电源/接地板上同步开关噪声.最后,不仅运用平面电路公式验证了新方法的精度,而且还通过分析高速MCM电源/接地板上同步开关噪声的两个例子,进一步阐明该方法的精度高、效率高特点.     

高速PCB镜像层设计

在高速多层PCB上,镜像层在噪声控制方面起着重要作用.良好的镜像层设计可以降低杂散电感引起的噪声,有助于控制串扰、反射和电磁干扰.本文结合作者的实际设计重点探讨了局部接地层的应用,并通过一个数模混合电路实例给出了一种镜像层分割法以及一些实践中需要注意的问题.     

片上电磁干扰感应阵列的设计与FPGA验证

测量EMI在片上电源分配网络中的二维分布,对研究集成电路的电磁抗扰性非常重要,能用于验证电磁抗扰模型的正确性。提出的片上电磁干扰感应阵列(OCEMISA)是一种测量EMI在电源分配网络上二维分布的测量方法。OCEMISA包含数个感应单元,在电源分配网络上产生开关噪声作为反馈信号,其频率各不相等,且只受局部电源电压的影响。用频谱分析仪经由电源引脚探测反馈信号,观察其特征频率随EMI的变化,计算感应单元所在位置EMI的电压分量,并采用FPGA验证OCEMISA的基本功能。     

Modeling of striplines between a power and a ground plane

In this paper, a stripline model is presented for coupled signal lines routed between a power and a ground plane based on multiconductor transmission line (MTL) theory. Through a suitable diagonalization of the MTL equations for striplines, the transverse electromagnetic (TEM) parallel-plate mode is decoupled from the stripline mode. In this way, stripline models that are obtained assuming ideal planes at ground potential can be extended to take into account the nonideal behavior of the planes. The presented model is applied to represent mode conversion due to vias, holes in the reference planes, and terminations of the stripline. Influence of inhomogeneous media is discussed.     

基于补偿原理的逆变器EMI抑制方法研究

由于逆变器电源对输出接地电容的限制,对严重的共模电磁干扰难以用大容量的共模滤波器抑制共模噪声。文章介绍了一种新型的基于噪声电流补偿原理的电力电子装置无源干扰抑制技术,探讨了不同方案实现对共模噪声电流的补偿,并在一台DC/AC逆变器中进行了补偿测试。实验结果证实了该EMI抑制方法的有效性。     

浅谈对地环路的噪声抑制

通过分析噪声源经过地环路产生对负载骚扰的原因及途径，指明了抑制地环路电磁骚扰的几种有效途径及其应用，为提高系统的EMC能力提供参考。     

Quantifying SMT decoupling capacitor placement in dc power-busdesign for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach