Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V     

A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems

The 4:1-multiplexer reported here is based on a 21 GHz f_T 0.4 μm silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is provided. A phase control circuit permits the choice of the optimum clock phase for the first and the second multiplexer stages; an internal delay line is not necessary. The 4:1-multiplexer consumes about 1.8 W with a single supply voltage of -4.5 V     

43 Gb/s decision circuits in InP DHBT technology

Packaged master-slave D-flip-flops designed in InP DHBT technology with 150 GHz f/sub t/ and 180 GHz f/sub max/ are presented. Measurement results using a 43.2 Gb/s nonreturn to zero (NRZ), pseudo random binary sequence (PRBS) data (generated from 4 channels of 10.8 Gb/s, 2/sup 31/-1, PRBS data) and a 43.2 GHz clock, show a clock phase margin of 190/spl deg/. 2:1 Static frequency dividers designed using the D-flip-flops have been tested up to 50 GHz and show normal operation. These circuits are key building blocks in numerous front-end circuits used for 40 Gb/s optical communication systems.     

20-40 Gb/s 0.2-μm GaAs HEMT chip set for optical data receiver

Using our 0.2-μm AlGaAs-GaAs-AlGaAs quantum well high electron mobility transistor (HEMT) technology, we have developed a chip set for 20-40 Gb/s fiber-optical digital transmission systems. In this paper we describe five receiver chips: a limiting amplifier with a differential gain of 17 dB and a 3 dB bandwidth of 29.3 GHz, a 40 Gb/s clock recovery, a data decision and a 1:4 demultiplexer, both for bit rates of more than 40 Gb/s, and a static 1:4 divider with operating frequencies up to 30 GHz. All presented chips were characterized on wafer with 50-Ω coplanar test probes     

Silicon bipolar 1:16-demultiplexer for 10 Gbit/s fibre opticcommunication system

A 1:16-demultiplexer based on silicon bipolar 1:4-demultiplexer ICs, which include all requirements for system applications, has been designed and tested. The authors report the design of the 1:4-demultiplexer, which operates up to 14 Gbit/s, and experimental results for the 1:16-demultiplexer at 10 Gbit/s     

An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

A silicon bipolar IC for data regeneration and clock recovery which includes a phase/frequency detector (PFD), a quadrature voltage controlled oscillator (VCO), and an MS D-flipflop (DFF) is presented. The VCO is based on a modified two stage ring oscillator approach and presents a wide tuning range of 2-to-9 GHz. Data regeneration at 8 Gb/s (with the onchip VCO) and PFD operation up to 15 Gb/s (with an external VCO) are demonstrated. The IC for clock and data regeneration was fabricated with a 25 GHz f_T 0.4 μm emitter width bipolar process. The power dissipation is 2.25 W     

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mWbit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

This paper reports the first CMOS implementation of an 8:1 byte-interleaved multiplexer (byte-MUX) operating in the Gb/s region, together with an 8:1 bit-interleaved multiplexer (bit-MUX). A future generation 0.15-μm CMOS technology has been applied. Both chips use identical bit-MUX cores with a static shift-register architecture, and have ECL interfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW/GHz dependence on clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with a power dissipation of 118 mW. This revel of performance has been achieved by a novel row-column exchanger configuration, critical path reduction and precise clocking techniques utilized in the bit-MUX core, and the development of high-speed I/O buffers     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

2.5Gb/s Ga As MESFET定时判决电路

设计了 2 .5 Gb/ s光纤通信用耗尽型 Ga As MESFET定时判决电路 .通过 SPICE模拟表明恢复的时钟频率达2 .5 GHz,判决电路传输速率达 2 .5 Gb/ s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号 ,传输速率达 2 .5 Gb/ s     

Design and Implementation of Open‐Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual‐Mode Operation

This paper proposes an open‐loop clock recovery circuit (CRC) using two high‐Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual‐mode operation. The DR filters are fabricated to obtain high Q‐values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak‐to‐peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo‐random binary sequence (PRBS) data with a word length of 2³¹?1 are less than 2.0 ps and 0.3 ps, respectively. The peak‐to‐peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error‐free operation of the 40 Gb/s‐class optical receiver with the dual‐mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.     

Optical Clock Recovery Using a Polarization-Modulator-Based Frequency-Doubling Optoelectronic Oscillator

We propose and demonstrate a flexible optical clock recovery scheme using a polarization-modulator-based frequency-doubling optoelectronic oscillator (OEO). The proposed system can extract both prescaled clock and line-rate clock from a degraded high-speed digital signal using only low-frequency devices. A simple theory is developed to study the physical basis of the optical clock recovery. The OEO operation from a free-running mode to an injection-locking mode is investigated. The locking range is quantitatively predicted. An experiment is then implemented to verify the proposed scheme. A prescaled clock at 10 GHz and a line-rate clock at 20 GHz are successfully extracted from a degraded 20 Gb/s optical time-division-multiplexed (OTDM) signal. The locking range and the phase noise performance are also experimentally investigated. Clock recovery from data signals that have no explicit subharmonic tone is also achieved. The proposed system can be modified to extract prescaled clock and line-rate clock from 160 Gb/s data signal using all 40-GHz devices.      

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.     

2.5Gb/s单片时钟恢复数据判决与1:4分接集成电路的设计

用0.25μm CMOS工艺实现一个复杂的高集成度的2.5Gb/s单片时钟数据恢复与1:4分接集成电路.对应于2.5Gb/s的PRBS数据(231-1),恢复并分频后的625MHz时钟的相位噪声为-106.26dBc/Hz@100kHz,同时2.5Gb/s的PRBS数据分接出4路625Mb/s数据.芯片面积仅为0.97mm×0.97mm,电源电压3.3V时核心功耗为550mW.     

Injection-locked Fabry-Pe/spl acute/rot laser with electronic feedback for clock recovery from high-speed OTDM signals

We demonstrate the use of an injection-locked Fabry-Pe/spl acute/rot laser diode with electronic feedback for base-rate clock recovery in N/spl times/10 Gb/s optical time-division-multiplexing (OTDM) systems. Injection-locking enhances the resonance frequency of the laser and the electrical feedback achieves strong resonance at the base-rate frequency of the injected data streams, enabling ultrastable electrical clock signal generation at the base rate of 10 GHz. Experimental demonstrations for clock recovery at 10 GHz from 40-Gb/s OTDM data streams and 4-1 demultiplexing of the data using the extracted clock after fiber transmission is presented. The timing jitter measured in the recovered electrical clock is less than 0.25 ps.     

Ultrahigh-speed clock recovery with phase lock loop based onfour-wave mixing in a traveling-wave laser diode amplifier

A new phase lock loop (PLL) is proposed and demonstrated for clock recovery from an ultrahigh-speed time-division multiplexed (TDM) optical signal. A traveling-wave laser-diode amplifier (TW-LDA) is used as a phase detector, and the cross-correlation component between the optical signal and an optical clock pulse train is detected as a four-wave-mixing (FWM) signal generated in the TW-LDA. A timing clock from a TDM signal is extracted as a prescaled electrical clock, and this prescaled clock is directly recovered from a randomly modulated TDM optical signal. A prescaled 6.3 GHz clock is successfully extracted from a 100 Gb/s signal using the timing comparison output obtained as the cross-correlation between the optical signal and a short (<10 ps) 6.3 GHz optical clock pulse train in the generated FWM light. A comparison of the PLL phase noise with a previously reported gain modulation method is also shown, and the possibility of the Tbit/s operation of this PLL is also considered in the experiments     

High-speed, burst-mode, packet-capable optical receiver andinstantaneous clock recovery for optical bus operation

This paper describes an enhanced performance version of a high-speed burst-mode compatible optical receiver and its application to 622-Mb/s optical bus operation in conjunction with an instantaneous clock recovery scheme. The receiver is fabricated in a 12 GHz f_t silicon bipolar technology and consists of a differential transimpedance amplifier with an auto-threshold level controller and a high-speed quantizer. Using an InGaAs avalanche photodiode, the typical burst mode sensitivity is around -34 dBm (10^-9 BER) at bit rates up to 1.5 Gb/s with a dynamic range of 26 db for both pseudorandom and burst signals. The results using a laser beam modulated by a high-speed external modulator indicate that the receiver can be operated at bit rates higher than 2 Gb/s. With a worst-case self-resetting time <50 ns for the threshold control circuit, the receiver is usable for optical packet communication where data signals with varying optical power are employed. This receiver was demonstrated in a 622-Mb/s optical bus application where the clock signal was recovered from the packet data signal using a novel high-speed CMOS instantaneous clock recovery IC     

10Gb/s CMOS时钟和数据恢复电路的设计

介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.