Scaling silicon MOSFET's for 77 K operation

Using the gradual channel approximation and the velocity-field relationship appropriate to holes in silicon, the static characteristics of Si MOSFETs at 77 K are scaled from those at 300 K to provide similar static characteristics at the two temperatures. Compared to 300 K, the approximate scaling factors for 77 K are 1/4 for voltage, 1/3 for current, 1/12 for static power, 1/16 for dynamic power, and 1/20 for the delay-power product. At 77 K the transconductance is increased by 20% compared to room temperature. Agreement between theory and experiment on p-channel devices is good for channel lengths greater than about 5 μm but the agreement decreases with decreasing channel length. Because the drain voltage required for current saturation decreases with decreasing temperature, circuit operation at supply voltages below 1 V appears feasible     

Parasitic bipolar effects in submicrometer GaAs MESFET's

We report the observation for the first time of parasitic bipolar action in GaAs MESFET's. It manifests itself in the form of increased transconductance at higher drain voltage, abrupt change in output conductance (kink effect) around 4-V drain-source voltage, and a gate-voltage-dependent substrate current. These effects are explained by electron-hole pair generation in the high-field region at the drain. The holes generated are injected into the substrate where they form the base region of a parasitic lateral bipolar transistor. The effect also explains a new breakdown mechanism for short-channel enhancement-mode MESFET's.     

DC performance of deep submicrometer Schottky-gated n-channel Si:SiGe HFETs at low temperatures

N-type Schottky-gated Si:SiGe heterostructure field-effect transistors with physical gate lengths between 70 and 450nm are characterized over a wide temperature range (T=10 K...300 K) for low electric fields. The room-temperature maximum low-field transconductance increases 61% to 440 mS/mm at T=10 K for the 70-nm device. The minimum subthreshold slope is 14...19 mV/dec at T=10 K. The off-state currents I/sub OFF/ are limited by parallel conduction at high temperatures and by the gate leakage current at low temperatures. Substrate leakage currents are found to be due to generation of carriers within the drain/substrate depletion layer and only make a minor contribution to I/sub OFF/. Operation of the devices at the lowest temperature is found to result in the occurrence of the floating-body kink effect, as a consequence of substrate freeze-out and subsequent self-biasing by impact ionization currents. Low temperature characteristics exhibit a nonlinear low-field drain current dependence on the drain voltage, due to the presence of parasitic Schottky source/drain contacts. An extraction method for access resistance consistent with this phenomenon is presented.     

GaAs MESFET低温性能实验

本文介绍了在低温下,对GaAs MESFET(包括12GHz低噪声器件、双栅器件、功率器件及振荡用器件)所进行的性能测量与分析。在218K(-55℃)下,上述各类器件的跨导g_m相对于室温可增加5～8％,器件的C_(gs)可减少20～50％,器件的寄生电阻R_s和R_d可减少15～40％,R_g也存在缓慢下降的趋势。 文章还给出了低温下低噪声GaAs MESFET放大器的噪声、增益—温度曲线。在218K下,放大器的噪声相对室温可下降1dB左右,单级增益相对室温可增加1～1.5dB,即在低温表现出良好的微波性能。     

Closed-form breakdown voltage model for PD SOI NMOS devices considering impact ionization of both parasitic BJT and surface MOS channel simultaneously

This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT.     

GaAs光导开关暗态击穿原因分析

光导开关(PCSS)在暗态耐压测试中耐压值低于理论值.根据GaAs材料特性,分析了暗态下光导开关的击穿机理.指出碰撞电离与电流控制负微分迁移率效应是导致开关击穿的直接原因.使用Silvaco半导体仿真软件对模型进行了模拟计算,结果表明温度显著影响电场、载流子浓度分布,引起碰撞电离等效应加剧,造成器件耐压值偏低.仿真结果与实验值基本相近,室温下耐压水平为33～40 kV/cm.光导开关击穿特性与温度密切相关,改善光导开关散热条件可提高开关耐压水平.     

Comparison between wurtzite phase and zincblende phase GaN MESFETsusing a full band Monte Carlo simulation

Cutoff frequency, breakdown voltage, and the transconductance of wurtzite and zincblende phase GaN MESFETs have been calculated using a self-consistent, full band Monte Carlo simulation. The effect of interface states on the device performance is modeled by including uniformly depleted regions at the device surface under the passivation layers. It is found that the drain current increases gradually with increasing drain-source voltage at the onset of breakdown for both phases. The calculated breakdown voltage for the wurtzite device is considerably higher than the breakdown voltage calculated for the zincblende device. On the other hand, the zincblende device is calculated to have higher transconductance and cutoff frequency than the wurtzite device. The higher breakdown voltage of the wurtzite phase device is attributed to the higher density of electronic states for this phase compared to the zincblende phase. The higher cutoff frequency and transconductance of the zincblende phase device is apparently due to the greater electron velocity overshoot for this phase compared to that for the wurtzite phase. The maximum cutoff frequency and transconductance of a 0.1 μm gate-length zincblende GaN MESFET are calculated to be 220 GHz and 210 mS/mm, respectively. The corresponding quantities for the wurtzite GaN device are calculated to be 160 GHz and 158 mS/mm     

Temperature dependence of DC and RF characteristics ofAlInAs/GaInAs HBT's

Device characteristics of compositionally graded AlInAs/GaInAs heterojunction bipolar transistors (HBTs) measured and analyzed from cryogenic temperatures up to 250°C are discussed. Excellent stability in DC and RF performance is observed at elevated temperatures, which is desirable for high-speed and high-density integrated circuit applications. DC current gain exhibits about 10% variation over the entire measured temperature range. F_T and f _max at 125°C decreased by approximately 10% from their room-temperature values while improving steadily when the device was cooled down to near-liquid-helium temperature, the common-emitter breakdown voltage is 8.0 V at room temperature and reduces to 7.5 V at 125°C. Likewise, the collector-base breakdown voltage and the base-emitter breakdown voltage reduce by about 0.5 V over the same temperature range. The breakdown voltages increase significantly at cryogenic temperatures. The low turn-on voltage and excellent low-temperature characteristics make the AlInAs/GaInAs HBT attractive for cryogenic applications     

Enhanced Gate Swing in InP HEMTs With High Threshold Voltage by Means of InAlAsSb Barrier

We demonstrated the suitability of the InP HEMTs with the InAlAsSb Schottky barrier to realize the high threshold voltage (enhancement mode), low gate current, and low power consumption. This quaternary compound material increases the conduction band discontinuity to the InGaAs channel by introducing only 10% of antimony to InAlAs. The gate current is reduced by an order of the magnitude (or even more) at gate voltage range from 0.4 to 0.8 V. On the other hand, the large conduction band discontinuity causes larger parasitic source and drain resistance, which decreases the extrinsic transconductance. Nevertheless, the high-frequency performance is comparable to the device with the conventional InAlAs barrier layer. Therefore, the InAlAsSb barrier is a promising option for logic applications, which requires reduced gate current. FETs, gate current, high-electron mobility transistors (HEMTs), high frequency.     

Temperature dependence of electroluminescence of Er ions in tunnel diodes based on (111)Si:(Er,O)

Electroluminescence and current-voltage characteristics of tunnel diodes obtained by implantation of Er, O, and B ions into n-Si(111) with the subsequent heat treatment are investigated in a temperature range of 80–300 K in the breakdown mode. The observed increase in electroluminescence intensity with temperature for Er ions is caused by thermal emptying of the traps that captured the holes in the n-region of the diode at low temperatures. This emptying leads to a variation in the breakdown characteristics. It is shown that some of the traps at low temperatures retain the charge captured even after the voltage applied to the diode is switched off. This circumstance gives rise to the peculiar memory effect in the structures investigated.     

Electrical switching in single crystal VO2

I–V characteristics of single crystal vanadium dioxide has been measured using a constant current source in the ambient temperature region 220–325°K. The temperature of the crystal surface has also been measured. It is observed that the switching voltage (V_th) increases but the current at switching (I_th) decreases with decreasing temperature, giving a temperature independent threshold power (V_th × I_th). At switching, the temperature of the crystal surface increases only by 3–6°K above ambient for different ambient temperatures. These results can be qualitatively explained by assuming that a filament (channel) is formed before switching. The switching occurs when the temperature of this filament of finite width approaches the semiconductor-metal transition temperature. The initial width of the channel at switching decreases with decreasing temperature and at a given ambient temperature the channel width increases with increasing current in the post breakdown region.     

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

Comparative study of drift region designs in RF LDMOSFETs

Systematic investigation of the drift region design of the RF LDMOSFET in terms of breakdown voltage, on-resistance, transconductance, capacitance and hot-carrier effects is presented. The incorporation of a source field plate allows for an increase of drift dose for a given breakdown voltage, which eases the tradeoff between the breakdown voltage and on-resistance, and the breakdown voltage and transconductance. However, the increased dose can significantly degrade hot-carrier reliability. A step-drift has enhanced hot-carrier immunity and lower capacitance, but, at the cost of increased on-state resistance and lower transconductance. Furthermore, a second origin of hot carriers is reported in the step-drift design, which may cause damage in the drift region. A deeper drift region design, which does not require an additional mask in comparison to the step-drift design, is investigated. The proposed approach shares all the advantages provided by the field plate design. Moreover, the lower concentration in the new drift region design leads to enhanced hot-carrier immunity.     

A model for anomalous short-channel behavior in submicron MOSFETs

Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel     

High-transconductance insulating-gate InP/InGaAs buried p-bufferDH-MODFETs grown by MOVPE

Buried p-buffer double heterostructure modulation-doped field-effect transistors (BP DH-MODFETs) with an InGaAs quantum-well channel were fabricated with high transconductance and good breakdown voltage, by placing the metal gate directly on Fe-doped InP insulating layer. Excellent extrinsic DC transconductance of 560 mS/mm and a high gate-to-drain diode breakdown voltage (greater than 20 V) were achieved at room temperature with FETs of 1.2-μm gate length. Unity currently gain cutoff frequency f_T of 24 GHz and maximum oscillation frequency f_max of 60 GHz were demonstrated for a drain to source voltage V_DS=4 V, which corresponds to an average electron velocity of 2.2×10⁷ cm/s in the quantum well     

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

High-voltage TFT fabricated in recrystallized polycrystallinesilicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 μm. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage     

一种新型的分段曲率补偿带隙基准源设计

针对传统的带隙基准源曲率补偿效果较差的问题,采用两路跨导放大器设计了一种新型的分段曲率补偿的带隙基准源。其中一路跨导放大器比较三极管的发射极-基极电压VEB和一个粗略的基准电压,在低温段产生随温度升高近似成指数减小的电流;另一路跨导放大器比较VEB和另一个粗略的基准电压,在高温段产生随温度升高近似成指数增大的电流,对传统的电流型带隙基准源进行精确的分段曲率补偿。基于TSMC 0. 18μm CMOS工艺,对电路进行设计和仿真。仿真结果表明,3. 3 V电源电压时,在-40^+150℃温度范围内,温度系数为1. 84×10^-6/℃,低频时的电源抑制比为-98. 3 d B,线性调整率为0. 0047%。