Terrain height measurement accuracy of interferometric syntheticaperture radars

Presents a simple expression for the accuracy with which an interferometer synthetic-aperture radar (IFSAR) can measure terrain elevation. The expression, derived analytically and confirmed by Monte Carlo simulation, accounts for thermal noise, resolution cell size, terrain slope and roughness, volume scattering above the terrain, radar-terrain geometry, interferometer baseline, and radar frequency. This paper takes a “glint” approach to assessing the impact of scatterers distributed in angle. The results show that there is a residual uncertainty in the height of a pixel due to its angular extent, even when the signal-to-noise ratio is very large. The analysis identifies an optimum range resolution for minimizing the height uncertainty for a particular terrain slope     

Quadrature bandpass ΔΣ modulation for digital radio

A quadrature bandpass ΔΣ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward “complex A/D conversion” of an image reject mixer's I and Q, outputs. Quadrature bandpass ΔΣ modulators provide superior performance over pairs of real bandpass ΔΣ modulators in the conversion of complex input signals, using complex filtering embedded in ΔΣ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-μm CMOS process is 2.4×1.8 mm²      

Zero-input oscillation bounds in a bandpass ΣΔmodulator

Sufficient conditions for the state-variables of zero-input oscillations of a bandpass ΣΔ modulator structure to remain within a prescribed square region in the state-space are derived for the full range of parameter values of the digital resonator within the modulator     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

The experimental determination of equivalent networks for a coaxial line to helix junction

Equivalent networks were determined for a right angle transition between a coaxial line and a shielded helix. By employing a movable mercury short on the helix it was possible to determine these equivalent circuits through the use of well-known microwave measurement techniques. Utilizing the possible physical connection which might exist between the junction and its equivalent circuit, an attempt was made to measure quantitatively the effect of varying various parameters in the junction. For the limited number of cases studied, no simple connection between the elements of the equivalent circuit and the physical parameters of the junction was discovered. Although the results for the equivalent networks were very sensitive to small experimental errors, by using these networks it was possible to calculate reasonably accurate values of input impedence in the coaxial line for known impedance terminations on the helix.     

Design and realization of a digital ΔΣ modulator forfractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital ΔΣ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital ΔΣ modulation to other applications of ΔΣ modulation where the literature is more complete. The paper then presents a digital ΔΣ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset     

Reliable analysis of settling errors in SC integrators: applicationto ΣΔ modulators

A study is presented into the transient response of SC integrators considering amplifier finite bandwidth, slew-rate, and parasitic capacitors during, unlike previous models, both the integration and sampling phases. The model is validated by experimental results on a second-order ΣΔ modulator and provides more reliable estimations of the defective settling in high-speed designs than previously reported models     

A CMOS monolithic ΔΣ-controlled fractional-N frequencysynthesizer for DCS-1800

A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm². To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints     

An eighth-order bandpass ΔΣ modulator for A/Dconversion in digital radio

This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-μm BiCMOS process and occupies an active area of 1.7 mm². Operating from ±2.5-V supplies, the fabricated prototype exhibits stable behaviour and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order single-bit bandpass delta-sigma modulation     

A quadrature data-dependent DEM algorithm to improve imagerejection of a complex ΣΔ modulator

A dynamic element matching (DEM) algorithm is presented that is controlled by the quadrature output data of a complex sigma-delta modulator. This DEM technique is used to correct the gain and phase errors between the circuits in the in-phase and quadrature-phase feedback paths of the modulator. The key feature of this DEM technique is that it does not cause leakage of high-frequency quantization noise in the signal band, as encounters with the periodic or pseudorandom DEM techniques. No test signal is required to measure the gain and phase errors, and as the DEM circuit is operating continuously, it compensates for changes in, e.g., temperature and supply voltage. A 0.35-μm CMOS prototype chip has been designed to test the DEM circuit. A batch of 38 measured samples shows a typical mismatch-independent image rejection ratio of 63 dB with DEM     

Dynamic range extension technique for high-order ΣΔADCs by digital level control

A new architecture is presented for a high-order multi-bit ΣΔ ADC which does not require a precision multi-bit DAC in the feedback loop. Local digital level control is employed to extend integrator output dynamic range. A prototype fourth-order modulator is simulated with circuit non-idealities, showing an SNR of ~110 dB     

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-bthird-order ΔΣ modulator

A 1.1-GHz fractional-N frequency synthesizer is implemented in 0.5-μm CMOS employing a 3-b third-order ΔΣ modulator. The in-band phase noise of -92 dBc/Hz at 10-kHz offset with a spur of less than -95 dBc is measured at 900.03 MHz with a phase detector frequency of 7.994 MHz and a loop bandwidth of 40 kHz. Having less than 1-Hz frequency resolution and agile switching speed, the proposed system meets the requirements of most RF applications including multislot GSM, AMPS, IS-95, and PDC     

A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dBdynamic range

A CMOS ΣΔ modulator for speech coding with continuous-time loopfilter is presented. Compared to switched-capacitor implementations, the relaxed bandwidth requirements of the active elements of the loopfilter reduce the power consumption. Furthermore, the need for an antialiasing filter at the modulator input is eliminated. A fourth-order, 64× oversampling ΣΔ modulator for application in portable telephones was designed and shows 80 dB dynamic range over the 300-3400 Hz voice bandwidth. Its input is directly connected to the microphone (maximum 40 mV_RMS). Total harmonic distortion (THD) is below -70 dB at 95 μA current consumption from a 2.2 V supply voltage. The active die area of the modulator is 0.5 mm² in a standard 0.5-μm CMOS process     

A 1.8-V ΔΣ modulator interface for an electretmicrophone with on-chip reference

The design of a delta-sigma (ΔΣ) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth-order ΔΣ ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption     

Reconstruction of oversampled band-limited signals fromΣΔ encoded binary sequences

Considers the application of ΣΔ modulators to analog-to-digital conversion. The authors have previously shown that for constant input signals, optimal nonlinear decoding can achieve large gains in signal-to-noise ratio (SNR) over linear decoding. The present paper shows a similar result for band-limited input signals. The new nonlinear decoding algorithm is based on projections onto convex sets (POCS), and alternates between a time-domain operation and a band limitation to find a signal invariant under both. The time-domain operation results in a quadratic programming problem. The band limitation can be based on singular value decomposition of a certain matrix. The authors show simulation results for the SNR performance of a POCS-based decoder and a linear decoder for the single loop, double loop and two-stage ΣΔ modulators and for a specific fourth-order interpolative modulator. Depending on the modulator and the oversampling ratio, improvements in SNR of up to 10-20 dB can be achieved     

The interferometric mirage effect method: The determination of the thermal diffusivity of CdMnTe

A Michelson interferometer was used as a precise detector in the Mirage effect configuration in order to determine the thermal diffusivity of the diluted magnetic semiconductor Cd_1−xMn_xTe, in the concentration range 0<x<0.6 at room temperature. This zinc-blende ternary alloy exhibits an almost linear behavior of the thermal diffusivity as a function of Mn concentration. This trend is similar to that of the energy gap against Mn concentration, which increases linearly as the nominal x value increases. The latter result was tested by electrolytic electroreflectance measurements.     

Broad-band determination of the FET small-signal equivalent circuit

A method to determine the broadband small-signal equivalent circuit of field-effect transistors (FETs) is proposed. This method is based on an analytic solution of the equations for the Y parameters of the intrinsic device and allows direct determination of the circuit elements at any specific frequency or averaged over a frequency range. The validity of the equivalent circuit can be verified by showing the frequency independence of each element. The method can be used for the whole range of measurement frequencies and can be applied to devices exhibiting severe low-frequency effects     

基于ΣΔ调制的D类放大器系统设计与仿真

针对传统D类放大器脉宽调制技术引起的电磁干扰问题,将一个5阶低通ΣΔ调制器应用于一种带反馈闭环结构的D类放大器中。通过建立ΣΔ调制D类放大器的非理想模型,考察输出信号的功率谱特性。仿真分析表明,该模型能够有效抑制低频段的噪声和谐波失真,在基带内实现较高的信噪比,应用于D类功放,与传统脉宽调制方式相比,有效地改善电磁干扰性能。     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

Effects of non-ideal Hadamard modulators on the performance ofΠΔΣ ADC

A non-ideal Hadamard modulator in the front-end of ΠΔΣ ADC can be modelled as an ideal Hadamard modulator with gain error in parallel with an offset error. The effects of non-ideal Hadamard modulators can be partially removed by using chopper stabilisation and adaptive channel gain equalisation