Neutral electron trap generation under irradiation in reoxidizednitrided gate dielectrics

In this study we report for the first time results on neutral electron trap generation in reoxidised nitrided oxide dielectrics under various radiation doses and bias conditions and compare the results with the conventional oxides. We see very little electron trap creation in RNO dielectrics for radiation doses up to 5 Mrad (Si) and for bias fields up to ±2.5 MV/cm. We explain our results in RNO and oxide dielectrics using a three step defect creation model     

Reliability issues in submicron MOSFETs with oxynitride gate dielectrics

A review of critical reliability issues in submicron MOSFETs with oxynitride gate dielectrics is presented. We have focussed our attention on: substrate and gate currents in short channel MOSFETs, hot carrier induced MOSFET degradation under DC and AC stress, gate-induced drain leakage current and its enhancement due to stress, neutral trap generation due to electrical stress and degradation of analog MOSFET parameters. We have also discussed the problems of radiation induced neutral trap generation and boron penetration through the gate dielectric, which arise due to the advanced processing techniques utilized in submicron MOSFET processing. It is concluded that the use of oxynitride gate dielectrics can effectively solve several reliability issues encountered in scaling down MOSFETs to submicron dimensions.     

Study of interface state generation in thin oxynitride gate dielectrics under hot-electron stressing

The hot-electron-induced interface state generation in thin ( approximately 8.6 nm) oxynitride films prepared by rapid thermal reoxidation (RTO) of rapidly thermal nitrided (RTN) SiO/sub 2/ have been studied. Both MOS capacitors and MOSFETs were used as testing devices. For MOSFETs charge-pumping current I/sub cp/ measurement was performed to monitor the increase Delta D/sub it/ of interface state density. It is found that the optimised RTN and RTO processes could produce devices with a significantly improved resistance against the hot electron-induced interface state generation.<>     

Comparison of electrical and reliability characteristics ofdifferent 14 Å oxynitride gate dielectrics

A comparison of RTNO, N₂O and N₂O-ISSG ultrathin oxynitride gate dielectrics fabricated by combining a remote plasma nitridation (RPN) treatment with equal physical oxide thickness of 14 Å is explored. The N₂O-ISSG oxynitride gate dielectric film demonstrates good interface properties, higher mobility and excellent reliability. This film by RPN treatment is thus attractive as the gate dielectric for future ultra-large scale integration (ULSI) devices     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

Polarity dependence of charge to breakdown and interface state generation of oxynitride gate dielectrics prepared by rapid thermal processing

MOS devices were fabricated with dry thermal oxides, nitrided oxides and annealed nitrided oxides. The anneals were performed in O/sub 2/ or N/sub 2/ ambients using rapid thermal processing. Charge to breakdown, Q/sub bd/, and interface state generation, Delta D/sub it/, for these devices were studied using Fowler-Nordheim electron injection. The gate bias polarity dependence of Q/sub bd/ and Delta D/sub it/ was investigated. A model is proposed to explain the observed dependence of these quantities on the polarity of injection and process parameters.<>     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO/sub 2/. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO/sub 2/ films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300/spl deg/C in crystallization temperature compared to HfO/sub 2/. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (/spl sim/14) is larger than that of HfO/sub 2/ (/spl sim/7.8). HfON dielectrics exhibit /spl sim/10/spl times/ lower leakage current (J) than HfO/sub 2/ for the same EOTs before post-metal anneal (PMA), while /spl sim/40/spl times/ lower J after PMA. The improved electrical properties of HfON over HfO/sub 2/ can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (/spl Delta/V) of HfON capacitor was found to be slightly larger than that of HfO/sub 2/. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm/sup 2//Vsec. By high temperature forming gas anneal at 600/spl deg/C, mobility improved up to 256 cm/sup 2//Vsec.     

Short-channel MOSFETs with oxynitride gate dielectrics fabricated using multiple rapid thermal processing

Short-channel MOSFETs with superior thin gate dielectrics have been successfully fabricated using multiple reactive rapid thermal processing of thermal oxides. The gate dielectrics are produced by rapid thermal nitridation (RTN) of thin thermal oxides in pure NH/sub 3/ ambient followed by rapid thermal reoxidation (RTO) in O/sub 2/ ambient. Devices fabricated with RTO/RTN gate dielectrics exhibit improved hot electron induced degradation compared to those fabricated with pure oxides. In addition, the subthreshold leakage current level of RTO/RTN devices is as good as for standard oxide devices.<>     

Characterization of ultrathin gate dielectrics formed by in-situ steam generation with nitrogen postprocessing

We examined ultrathin films produced by in-situ steam generation (ISSG), ISSG with NO anneal, ISSG with remote plasma nitridation (RPN), and rapid thermal oxidation (RTO). Capacitance-voltage measurements performed on these films indicated an equivalent oxide thickness (EOT) in the range of 1.6–2.5 nm. The nitrogen postprocessing made it possible to achieve thinner EOTs while keeping theleakage current density below 10⁻² A/cm² at V_g=−1.5 V. Total x-ray fluorescence (TXRF) analysis on the films yielded a transition metal concentration less than 5×10¹⁰ atoms/cm². Atomic force microscopy (AFM) measurements yielded microroughness values of 0.18–0.2 nm, which were conformal to the starting material surface microroughness. High-resolution transmission electron microscopy (HRTEM) images showed physical thicknesses ranging from 2.0–3.0 nm, which were used, in conjunction with the EOTs, to calculate effective dielectric constants for the films. Low energy (500 eV) secondary ion mass spectrometry (SIMS) measurements performed on the ISSG + NO and ISSG + RPN films showed sharply different [N] profiles.     

Mobility improvement of n-MOSFET's with nitrided gate oxide bybacksurface Ar+ bombardment

Low-energy (550 eV) argon-ion beam was used to bombard directly, the backsurface of nitrided n-MOSFET's after the completion of all conventional nMOS processing steps. The interface characteristics and inversion layer mobility of the MOS devices were investigated. The results show that, as bombardment time increases, interface state density and fixed charge density decrease first, and then the change slows down or even turns around. Correspondingly, the carrier mobility and drain conductance of the MOS devices are found to enhance first, and then saturate or turn around. Therefore, this simple technique, which is readily compatible with existing IC processing, is effective for restoring some of the lost device performance associated with gate-oxide nitridation     

Influence of holes on neutral trap generation

Using a newly proposed method for estimating the neutral trap density, generation characteristics of the neutral trap during various stress types have been investigated. From the analysis of the trap-generation kinetics, two types of trap generation closely related to holes have been identified. At the first stage of stress application, holes interact with the pre-existing structural origins of the neutral traps, then the neutral traps are generated. Influence of hole energy on this type of trap generation is also identified. After that, as holes pass, they also create the structural origins of the traps. The holes interact with these structural origins and the neutral traps are generated as a secondary effect. Thus, the increase in the neutral trap density shows up clearly with increase in the hole fluence. The stress-strength dependence of the increase in the neutral trap density can also be interpreted in terms of the influence of hole energy on the trap generation     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

Application of non-linear optical second harmonic generation and X-ray absorption and spectroscopies to defect related properties of Hf silicate and Hf Si oxynitride gate dielectrics

Three different Hf oxide based dielectrics have emerged as viable candidates for applications in advanced ULSI devices. This article focuses on two of these: (i) phase separated Hf silicates with (i) 70–85% nano-crystalline HfO₂ with a nano-grain size <2 nm, and 15–30% ～2 nm non-crystalline SiO₂ inclusions, and (ii) Hf Si oxynitride alloys, the most promising of which has a composition, (HfO₂)_0.3(SiO₂)_0.3(Si₃N₄)_0.4 designated as 3/3/4 Hf SiON. X-ray absorption spectroscopy has been applied to identification of defect associated with vacancy structures in phase separated silicates, and network disruption defects in the Hf Si oxynitrides. Optical second harmonic generation is introduced in this article for the first time as a non-invasive approach for detecting macroscopic strain, that is shown to be absent in these low defect density dielectrics, the phase separated Hf silicates, and Hf Si oxynitrides, but present in HfO₂ films, and Hf silicates with lower HfO₂ content, e.g., the 40% HfO₂ film of this article.     

Electrical characteristics of oxynitride gate dielectrics prepared by rapid thermal processing of LPCVD SiO/sub 2/ films

High-quality oxynitride gate dielectrics have been fabricated by rapid thermal processing of LPCVD SiO/sub 2/ in reactive ambients (NH/sub 3/ and O/sub 2/). The as-deposited CVD oxides of 200 AA in thickness show no early breakdowns. The breakdown distribution becomes tighter, the interface state density is reduced, and the interface endurance property is improved after rapid thermal nitridation and reoxidation.<>     

Improved method for the oxide thickness extraction in MOSstructures with ultrathin gate dielectrics

An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique and of Vincent's method is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm to 1.8 nm     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

高k栅介质原子分辨率的电镜表征：研究进展和展望

随着特征尺寸不断缩小,CMOS器件已步入纳米尺度范围,因此纳米尺度器件的结构表征变得尤为关键。完备的半导体器件结构分析,要求确定原子位置、局部化学元素组成及局域电子结构。高分辨（分析型）透射电镜及其显微分析技术,能够提供衍衬像（振幅衬度像）、高分辨像（相位衬度像）、选区电子衍射和会聚束电子衍射、X射线能谱（EDS）及电子能量损失谱（EELS）等分析手段,已作为半导体器件结构表征的基本工具。配有高角度环形暗场探测器的扫描透射电镜（STEM）,因其像的强度近似正比于原子序数（Z）的平方,它可在原子尺度直接确定材料的结构和化学组成。利用Z-衬度像配合高分辨电子能量损失谱技术,可确定新型CMOS堆垛层中的界面结构、界面及界面附近的元素分布及化学环境。近年来新开发的球差校正器使得HRTEM／STEM的分辨率得到革命性提高（空间分辨率优于0．08nm,能量分辨率优于0．2eV）,在亚埃尺度上实现单个纳米器件的结构表征。装备球差校正器的新一代HRTEM和STEM,使得高k栅介质材料的研究进入一个新时代。本文首先介绍了原子分辨率电镜（HRTEM和STEM）的基本原理和关键特征,对相关高分辨谱分析技术（如EDS和EELS）加以比较;然后综述了HRTEM／STEM在高k栅介质材料（如铪基氧化物、稀土氧化物和外延钙钛矿结构氧化物）结构表征方面的最新进展;最后对亚埃分辨率高k栅介质材料的结构表征进行了展望。     

New insights in the relation between electron trap generation andthe statistical properties of oxide breakdown

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q_BD-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q_BD for ultrathin oxides     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.