On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature lower than 600°C, are now largely used in many applications, particularly in large area electronics. The reliability of these TFT's under different electrical conditions is then questionable. In this work, Gate bias stress is studied in two types of polysilicon TFT's originated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. As this hydrogenation step is known to improve the TFT's performances but to introduce unstability, the unhydrogenated TFT's are expected to be more stable. The behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TFT's fit with the known model of the n-channel c-Si MOSFET's bias stress. The behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon.     

Effects of mechanical strain on laser crystallized polysilicon thin film transistors and ring oscillators fabricated on stainless steel foil

In this paper the influence of mechanical tensile strain on the performance of thin film transistors (TFTs), with various channel geometries, and of ring oscillators, with 3, 7, 11, 21, and 51 number of stages and device channel lengths of 1, 4, and 8 μm, fabricated on stainless steel foil substrate is investigated. TFT parameters such as field effect mobility, threshold voltage, subthreshold slope, leakage and gate current for both n-channel, and p-channel TFTs are studied at various longitudinal tensile strain levels. For strain levels from 0.0% to 0.5%, the field effect mobility of n-channel TFTs increases while that of p-channel ones decreases as the longitudinal tensile strain increases. The field effect mobility, of both n-channel and p-channel TFTs, becomes independent of longitudinal tensile strain at strain levels greater than 0.5%. Threshold voltage and subthreshold slope of p-channel TFTs increases while that of n-channel ones does not follow a specific trend. The leakage current of both type devices tends to decrease by increasing the longitudinal tensile strain. The propagation delay, per inverter stage of a ring oscillator, is investigated at different supply voltages and tensile strain levels. The propagation delay of inverters with longer device channel length (?4 μm) tends to decrease while that of shorter length tends to increase as the longitudinal tensile strain increases.     

Enhanced channel mobility in polysilicon thin film transistors

Due to scattering by charged grain boundaries, carrier mobility μ in the channel of polysilicon thin film transistors (TFT) is usually much lower than the bulk silicon value. We have studied a series of _p-channel TFT devices with varying gate oxide thicknesses d_ox and found that CL shows a strong increase when d_ox is reduced below 150 Å. We attribute this effect to the screening of the charged grain boundary by the gate conductor. The screening becomes effective when the characteristic length associated with the potential barrier at charged grain boundaries becomes comparable to the optical distance between the grain boundary charge and its mirror image in the gate electrode. From the known structure parameters the onset of the strong screening is estimated to occur at oxide thicknesses of about 100 Å     

Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm²/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.     

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (⩽600°C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity     

A physical model of floating body effects in polysilicon thin film transistors

Based on a closed form of the base–emitter voltage of the parasitic bipolar transistor, a physical model of floating body effects is proposed for polysilicon thin film transistors, which takes into account the polysilicon graded pn junction and the generation rate including the Poole-Frenkel effect. Simulated results by this model are in good agreement with experimental data. It is shown that the action of a parasitic bipolar transistor should be taken into account only when the channel length is short enough due to the much smaller carrier mobility in polysilicon compared with single crystalline silicon. Whereas, the parasitic bipolar transistor gain (β) increases sharply with decreasing the channel length when the channel length is less than 5 μm, which is due to the rapid increase of the base transport factor (_T).     

Low-frequency noise in low temperature unhydrogenated polysilicon thin film transistors

Low-frequency noise measurements are performed in two types of low temperature polysilicon thin film transistors (TFTs). For the first TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility fluctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the fluctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite different from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering.     

New selfalignment processes for amorphous silicon thin film transistors with polysilicon source and drain

New fabrication processes for selfaligned amorphous silicon TFTs are proposed. The TFTs have a polysilicon source and drain which are formed by ArF excimer laser annealing. They exhibit a field-effect mobility of 0.8 cm/sup 2//Vs, threshold voltage of 11 V, and on/off current ratio of higher than 10/sup 6/.<>     

Influence of rapid thermal and low temperature processing on theelectrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465°C. For the Si films annealed at 750°C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at λ=405 nm), the potential barrier height Φ_B due to the grains, and the field-effect mobility, μ_n,p, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called “grains” of the films annealed at 600°C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance     

Zapping thin film transistors

It was expected that hydrogenated amorphous silicon thin film transistors (α-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an α-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.     

Characteristics of thin film transistors fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition

Thin-film transistors (TFTs) fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition (PECVD) were characterized. The transistors were fabricated using a low temperature process (i.e., <- 700° C). The characteristics of the devices were found to improve as the deposition temperature of the polysilicon film increased. The best characteristics (μ _FE of 15 cm²/V _s andV _TH of 2.2V) were measured in the devices fabricated in the film deposited at 700° C. The devices fabricated in the PECVD polysilicon films were compared to those fabricated in polysilicon films deposited by thermal CVD in the same reactor in order to decouple the effect of the plasma. A coplanar electrode structure TFT with adequate characteristics (μ _FE of 8 cm²/V _s) was also demonstrated in the PECVD polysilicon films.     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

Self-patterning of high-performance thin film transistors

We have developed a technique for the preparation of thin film transistors (TFTs) through the self-patterning of various organic and inorganic materials via solution processing using a wide range of solvents. To obtain selectively self-patterned layers, we treated the oxide dielectric with two-phase patterned self-assembled monolayers of hexamethyldisilazane (HMDS) and octyltrichlorosilane. The conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonic acid) in water and the dielectric polymer poly(vinyl phenol) in propylene glycol methyl ether acetate were both selectively deposited and patterned on the HMDS regions with high-quality feature shapes. When source and drain electrodes were patterned on the bottom-gate oxide wafer, we also self-patterned organic and inorganic semiconductors around the channel (HMDS) regions. These TFT devices exhibited moderate to good electronic characteristics. This method has great potential for the economical full solution processing of large-area electronic devices. The selectivity in the patterning phenomena can be understood in terms of surface energy interactions.     

Gate-planarized organic polymer thin film transistors

We report in this paper the fabrication and characterization of a new gate-planarized organic polymer thin-film transistor (GP OP-TFT). We describe in detail the effects of the measurement procedure on the GP OP-TFT electrical characteristics and extracted parameters and show that it is extremely critical to carefully control the electrical measurement conditions to obtain accurate and meaningful results, before any material optimization is undertaken. We also describe the importance of normalization of electrical characteristics and extracted parameters for a proper comparison of different devices. Finally, we report and analyze the gate voltage and channel length dependence of the TFT field-effect mobility.     

Electronic characterization of double-gate thin film transistors

A method of determining the electronic parameters, i.e. the free charge carrier density, the surface state density and the bulk trap state density, of the semiconductor in double-gate thin film transistors is described. The method is based on a comparison of the calculated field-effect conductance with the observed drain current of the device. The theory is formulated such that it applies even though the semiconductor is thin compared with the effective Debye lengths. An illustrative example of the method applied to a CdSe double-gate thin film transistor is given.