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1.
黄平  吴景东 《微计算机信息》2007,23(14):191-192
SOC、嵌入式智能设备已经越来越广泛地应用于工业控制现场取代原来相对复杂的工控PC机。对于生产嵌入式智能设备而言,有时从成本和实用性角度考虑需要自行设计显示接口,本文就800*600*256色工控用TFTLCD显示接口提供一个廉价的可行性解决方案。  相似文献   

2.
基于FPGA高速图像数据的存储及显示设计   总被引:1,自引:0,他引:1  
设计了一种基于FPGA控制Nand Flash阵列实现高速流水线式存储的方案。设计利用FPGA作为主控制器,通过Camera Link输入通信接口将图像数据经过一/二级缓存写入Flash存储阵列中,并采用DMA传输技术将存储后的图像数据上传至计算机硬盘中作进一步处理;同时,利用SDRAM显存实时刷新数据,FPGA构造相应的VGA信号,最终实现100 MB/s图像数据的实时显示。  相似文献   

3.
有限的片外存储带宽是制约流处理器性能提升的瓶颈之一,流存储系统已经采用了多种方式来缓解这个问题,但当前的设计并没有充分考虑应用具体的访存模式对有效带宽利用率的影响.通过分析和实验,评估流存储系统主要设计参数对不同访存模式的优化效果;在此基础上针对不同的流访问并行度提出了相应的结构改进,加入宽发射和短作业优先调度支持,充分挖掘存储访问的局部性和并行性,改善了负载平衡,从而有效地提高了片外带宽的使用效率和流程序的整体性能.  相似文献   

4.
    
Ongoing transistor scaling and the growing complexity of embedded system designs has led to the rise of MPSoCs (Multi‐Processor System‐on‐Chip), combining multiple hard‐core CPUs and accelerators (FPGA, GPU) on the same physical die. These devices are of great interest to the supercomputing community, who are increasingly reliant on heterogeneity to achieve power and performance goals in these closing stages of the race to exascale. In this paper, we present a network interface architecture and networking infrastructure, designed to sit inside the FPGA fabric of a cutting‐edge MPSoC device, enabling networks of these devices to communicate within both a distributed and shared memory context, with reduced need for costly software networking system calls. We will present our implementation and prototype system and discuss the main design decisions relevant to the use of the Xilinx Zynq Ultrascale+, a state‐of‐the‐art MPSoC, and the challenges to be overcome given the device's limitations and constraints. We demonstrate the working prototype system connecting two MPSoCs, with communication between processor and remote memory region and accelerator. We then discuss the limitations of the current implementation and highlight areas of improvement to make this solution production‐ready.  相似文献   

5.
【目的】高性能计算技术在航空制造业应用不断深入,加快了科技进步的步伐,美国在此方面表现较为突出。相比之下,我国此方面能力较为薄弱,能力不足、不均衡问题较为突出,本文基于当前面临的问题和新的发展趋势,尝试提出一套建设框架和规划设计方法。【方法】本文分析了美国情况、国内同行业高性能计算基础设施情况,对航空制造业在高性能计算技术应用面临的问题进行了总结,对趋势进行了分析。【结果】结合问题和发展趋势,给出建设参考框架和规划设计方法,推动系统建设高质量发展。【结论】高性能计算机已经成为颠覆产品设计研发、引领创新的重要保障手段和技术,在当前航空制造业快速发展阶段,需推动快速建设,补齐短板,做好人才队伍的建设,实现行业/领域全面能力水平提升。  相似文献   

6.
杨相生 《计算机工程》2003,29(4):164-166
随着CPU的主频超越千兆赫,存储器技术逐渐成为计算机内部体系结构性能的瓶颈。如果配置足够容量的高速存储器,较低主频的CPU的运行速度完全可以超过较高主频的CPU。文章对RAM技术及其常规产品进行了充分的研究和探讨,并将研究的注意力主要集中在增加动态RAM的带宽技术上。  相似文献   

7.
本文介绍韩国三星公司1995年推出的动态存储器KM44C4100型芯片的特性和接口方法。结合在心电记录中的应用实例,研究了简化接口电路和降低功耗的途径。  相似文献   

8.
针对当前远程监护系统中的一些缺点,作者利用HPC的RAS,网络通信及串行通信功能,结合我国发达的公用电话网,成功地设计并实现了一套可以传输多种生理参数的远程监护系统。  相似文献   

9.
随着云计算技术的发展,高性能计算云(HPC in the Cloud)已得到学术界和产业界的关注。由于虚拟化技术带来的性能开销,高性能计算云面临着一些挑战。针对“高性能计算+云”的计算模式,分析了高性能计算云的优势,深入介绍了国内外基于基准测试的高性能计算云的性能评测、性能优化、能耗和成本效益等关键问题,得出了针对基准测试的高性能计算云研究的基本思路,并对当前面临的问题和今后的发展趋势进行了总结和展望。  相似文献   

10.
    
This special issue on the Pervasive Nature of HPC (PN-HPC) collects an extension of the most valuable works presented at the sixth Workshop on Models, Algorithms and Methodologies for Hybrid Parallelism in New HPC Systems (MAMHYP-22), held in Gdansk (Poland) in September 2022, jointly with the 14th conference on Parallel Processing and Applied Mathematics (PPAM-22). New original papers related to the workshop themes are also included. The final aim is to provide a glimpse of the current state of knowledge related to the development of efficient methodologies and algorithms for HPC systems with multiple forms of parallelism.  相似文献   

11.
物理不可克隆函数(Physical Unclonable Functions,PUF)可视为一种\"芯片指纹\",具有轻量级、不可预测、难以克隆等特性,已经成为物联网硬件安全机制的重要组成部分.然而,传统PUF的实现需要在硬件层面增加FPGA或专用集成电路,会增加硬件成本.对于数以亿计的现有物联网嵌入式设备,难以通过硬件改造来增加PUF安全属性.因此,从现有设备的硬件结构中挖掘固有PUF(Intrinsic PUF,IPUF)成为PUF研究与产业化的关键组成部分.本工作将对已有的IPUF,尤其是基于存储器的IPUF(Memroy-based Intrinsic PUF,MIPUF)相关工作进行系统综述,并针对IPUF在现有系统中的可实现性及未来的发展方向进行讨论,以推动该技术的工程应用.  相似文献   

12.
热轧精轧机换辊自动化控制系统研究   总被引:1,自引:0,他引:1  
基于武钢热轧厂1580mm热连轧精轧机工作辊快速换辊系统的应用,重点分析换辊自动化系统的工作原理,论述了快速换辊的控制思路和优化方法.实践证明,该系统运行稳定可靠,减少了换辊时间,最大程度地提高了换辊效率.  相似文献   

13.
The trend in the price of dynamic random access memory (DRAM) is a very important prosperity index in the semiconductor industry. To further enhance the performance of DRAM price forecasting, a hybrid fuzzy and neural approach is proposed in this study. In the proposed approach, multiple experts construct their own fuzzy multiple linear regression models from various viewpoints to forecast the price of a DRAM product. Each fuzzy multiple linear regression model can be converted into two equivalent nonlinear programming problems to be solved. To aggregate these fuzzy price forecasts, a two-step aggregation mechanism is applied. At the first step, fuzzy intersection is applied to aggregate the fuzzy price forecasts into a polygon-shaped fuzzy number, in order to improve the precision. After that, a back propagation network is constructed to defuzzify the polygon-shaped fuzzy number and to generate a representative/crisp value, so as to enhance the accuracy. A real example is used to evaluate the effectiveness of the proposed methodology. According to experimental results, the proposed methodology improved both the precision and accuracy of DRAM price forecasting by 66% and 43%, respectively.  相似文献   

14.
基于i860的存储器子系统设计   总被引:1,自引:0,他引:1  
微处理机系统中的存储器子系统设计对整个系统性能的高低有重要的影响,尤其当微处理器的主频越来越高时。本文结合实际例子,给出了一个基于i860处理器(40MHz)的主存设计方案,讨论了实际中需仔细考虑的因素。该设计可为其它高性能RISC系统设计提供参考。  相似文献   

15.
A novel operation mechanism of capacitorless SOl-DRAM (silicon on insulator dynamic random access memory) cell using impact ionization and GIDL (gated-induce drain leakage) effects for write "1" operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET (double-gate fin field effect transistor) cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read "1" and read "0" current is more than 9.38E5. Moreover, the cell has great retention characteristics.  相似文献   

16.
关于中央处理器-存储器集成的讨论   总被引:1,自引:1,他引:0  
在处理器运算速度持续提高的情况下,传统的存储器系统已经成为严重的性能瓶颈。中央处理器-存储器集成是一种有良好应用前景的新思路。通过一个简单的评价模型和模拟运行数据,分析了几种处理器-存储器集成方案的优劣,为未来的进一步研究提供参考。  相似文献   

17.
    
The China HPC TOP100 list, an annual report of the 100 most powerful high performance computing (HPC) systems installed in mainland China, has traced the rapid growth of HPC technology in China since its first publication in 2002. This paper introduces the China HPC TOP100 list and reviews the current status of HPC systems in China in terms of system features, manufactures, and areas of application using the data reported in the most recent list, published on November 1st, 2009. We provide further analysis, prediction of future trends, and directions of the development of HPC systems in China referencing historical data accumulated through archived TOP100 lists and other publically available information. We predict that the aggregated Linpack performance of the top 100 HPC systems will reach 10 PFlops in 2011, a single system with 10 PFlops peak performance will appear between 2012 and 2013, the aggregated performance of the top 100 systems will reach 100 PFlops in 2014, and a single system with 100 PFlops peak performance will appear around 2015.  相似文献   

18.
罗奎  严义 《计算机应用》2014,34(9):2738-2741
针对基于现场可编程门阵列(FPGA)的新型可编程逻辑控制器(FPGA based PLC)的在线监控问题,提出了泛化的基于FPGA技术对嵌入式片上系统(SoC)进行在线监控的方法。该方法设计了一个FPGA片上通信系统,系统内部固化基于UART的ModBus通信协议栈,通过串口与计算机上位机进行通信;采用双口RAM(DRAM)作为与监控对象间共享的数据缓存区,通过中断机制实现缓存数据的同步交换。性能分析结果表明,该方法将SoC处理监控通信的时间百分比降低至0.002%,确保了监控数据传送的实时性,且使SoC能够获得更佳控制性能。在Altera的cycloneⅡ系列芯片开发板上验证了方案的可行性。  相似文献   

19.
    
Memory access scheduling is an effective manner to improve performance of Chip Multi-Processors (CMPs) by taking advantage of the timing characteristics of a DRAM. A memory access scheduler can subdivide resources utilization (banks and rows) to increase throughput by accessing different DRAM banks in parallel. However, different threads running on different cores may exhibit different performance. One thread may experience starvation while the others are serviced normally. Therefore, designing a scheduler which reduces the unfairness in the DRAM system, while also improving system throughput on a variety of workloads and systems, is necessary. In this paper, a distributed fair DRAM scheduling for two-dimensional mesh network-on-chips (NoCs), called DFDS, is presented. The key design points in DFDS are: (i) assessing the total waiting cycles of a memory request in NoC and considering it as a metric in arbitration. For this purpose waiting cycles of a memory request are put in an additional flit in a packet and are updated while traversing the NoC, and (ii) proposing a semi-dynamic virtual channel allocation to provide in-order memory requests to memory controllers (MCs). Consequently, we use a simple scheduling algorithm in MCs, instead of complex algorithms. To validate our approach, we apply synthetic and real workload from Parsec benchmark suite. The results show effectiveness of our approach, as we reduce the waiting time of memory requests by up to 15%.  相似文献   

20.
传统上,HPC 与解决大规模科学计算和相应大数据紧密结合。伴随着物联网、移动互联网时代的到来,数据呈现出前所未有的爆炸式的增长,给人类对数据的利用方式提出了新的命题与挑战。2012 年,Hinton 采用深度学习的方法以巨大的优势摘取 ImageNet 的桂冠,让人类看到了海量数据与人工智能相结合的巨大价值。HPC 系统天然与深度学习无缝对接,本文将以高性能计算集群为基础,提供搭建一整套高性能的深度学习平台设计思路与实现,并以 Slurm 调度分布式 TensorFlow 进行海量数据的相关的测试实验。  相似文献   

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