基于现场可编程门阵列的新型可编程逻辑控制器在线调试技术

针对基于现场可编程门阵列(FPGA)的新型可编程逻辑控制器(FPGA based PLC)的在线监控问题,提出了泛化的基于FPGA技术对嵌入式片上系统(SoC)进行在线监控的方法。该方法设计了一个FPGA片上通信系统,系统内部固化基于UART的ModBus通信协议栈,通过串口与计算机上位机进行通信;采用双口RAM(DRAM)作为与监控对象间共享的数据缓存区,通过中断机制实现缓存数据的同步交换。性能分析结果表明,该方法将SoC处理监控通信的时间百分比降低至0.002%,确保了监控数据传送的实时性,且使SoC能够获得更佳控制性能。在Altera的cycloneⅡ系列芯片开发板上验证了方案的可行性。     

A scheduler ASIC for a programmable packet switch

While the Internet is successful in supporting traditional data-only traffic, an integrated services Internet is inevitable with the emergence of new applications such as voice, video, multimedia, and interactive video conferencing. Such an integrated services network should support a wide range of applications with diverse quality of service requirements and traffic characteristics. Provision for quality of service in packet networks in general, and in the Internet in particular, is the focus of most of the recent developments in switching and routing system design. We designed a generic, single-queue scheduler engine for use in a programmable packet switch/router to handle IP packets, ATM cells, or a combination of both. Comprising 275,000 gates, the 0.35-micron ASIC is incorporated into a prototype programmable packet switch     

KB-SCHED: Knowledge-based scheduler for complex and dynamic systems

Scheduling problems are becoming more and more complex everyday. This makes the current rules and algorithms difficult to comply with the requirements. New machines with the capabilities of processing more than one jobs is being developed. Sometimes one job is divided into parts and processed by more than one machine at the same time. These make the current algorithms insufficient. Artificial intelligence technologies, especially expert systems are proven to deal with such dynamic complex problems in several domains. In this study, an example of such a complex problem is introduced and knowledge-based scheduling for these kind of problems is elaborated with a real life industrial example.     

可编程微波炉控制器的设计

基于可编程逻辑器件EPM240T100C5,使用硬件描述语言VHDL,采用"自顶向下"的设计方法,编写一个微波炉控制器的芯片。介绍了微波炉控制器的设计思路与模块划分,应用Quartus II软件对每个模块和主程序分别进行了调试,并硬件下载到开发板上进行了模拟调试。     

A programmable text-editing system

A full-screen text-editor is described which has been augmented with a programming facility. The facility consists of an interpreter which inspects a program and generates output to drive the editor. This bridges the gap between text-editing and text-processing and allows the editor to carry out complicated operations. The features of the editor are described briefly, and the programming language employed by the interpreter is presented. Several applications are discussed to show the range and versatility of the system.     

A variable-precision square root implementation for field programmable gate arrays

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.Notation S_j square root digit of weight 2^–j - S _j {–1, 0, 1} - S[j] computed square root value as of stepj - S _j ^s sign bit in the representation ofS _j in sign and magnitude form - S _j ^m magnitude bit in the representation ofS _j in sign and magnitude form - w[j] residual at stepj in two's complement carry-save representation - a sum vector in the carry-save representation of 2w[j] - b carry vector in the carry-save representation of 2w[j] - a _i bit of weight 2^–i in the sum vector,a - b_i bit of weight 2^–i in the carry vector,b - T[j]=–S[j – 1]s_j – s _j ² 2^–(j+1) T _i bit of weight 2^–i inT     

FPGEN: A fast, scalable and programmable traffic generator for the performance evaluation of high-speed computer networks

Testing today’s high-speed network equipment requires the generation of network traffic which is similar to the real Internet traffic at Gbps line rates. There are many software-based traffic generators which can generate packets according to different stochastic distributions. However, they are not suitable for high-speed hardware test platforms. This paper describes FPGEN (Fast Packet GENerator), a programmable random traffic generator which is entirely implemented on FPGA (Field Programmable Gate Array). FPGEN can generate variable packet sizes and traffic with Poisson and Markov-modulated on-off statistics at OC-48 rate per interface. Our work that is presented in this paper includes the theoretical design of FPGEN, the hardware design of the FPGA-based traffic generator board (printed circuit board design and construction) and the implementation of FPGEN on FPGA. Our experimental study demonstrates that FPGEN can achieve both the desired rate and statistical properties for the generated traffic.     

基于DRAM、FPGA的专用LCD显示接口设计与实现

SOC、嵌入式智能设备已经越来越广泛地应用于工业控制现场取代原来相对复杂的工控PC机。对于生产嵌入式智能设备而言,有时从成本和实用性角度考虑需要自行设计显示接口,本文就800*600*256色工控用TFTLCD显示接口提供一个廉价的可行性解决方案。     

A programmable array processor architecture for flexible approximate string matching algorithms

Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don’t care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8–340 times faster execution than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024.     

A cautious scheduler for multistep transactions

Given a classC of serializable schedules, a cautiousC-scheduler is an on-line transaction scheduler that outputs schedules in classC and never resorts to rollbacks. Such a scheduler grants the current request if and only if the partial schedule it has granted so far, followed by the current request, can be extended to a schedule inC. A suitable extension is searched among the set of all possible sequences of the pending steps, which are predeclared by the transactions whose first requests have already arrived. If the partial schedule cannot be extended to a schedule inC, then the current request is delayed. An efficient cautiousCPSR-scheduler has been proposed by Casanova and Bernstein.This paper discusses cautiousWRW-scheduling, whereWRW is the largest polynomially recognizable subclass of serializable schedules currently known. Since cautiousWRW-scheduling is, in general, NP-complete as shown in this paper, we introduce, a subclass (namedWRW ^#) ofWRW and discuss an efficient cautiousWRW ^#-scheduler. We also show that the fixed point set of the cautiousWRW ^#-scheduler properly containsCPSR. Therefore, ourWRW ^#-scheduler allows more concurrency than anyCPSR- scheduler.This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under Grant No. A5240 and in part by the Ministry of Education, Science and Culture of Japan under Scientific Research Grant-in-Aid.     

A programmable shell and graphics system for forest stand simulation

Problems associated with transporting cumbersome, batch-run FORTRAN programs to an interactive microcomputer platform are common to many projects in ecological modelling. We describe the experience of modifying and enhancing ZELIG, a simulation model of forest stand dynamics, for use as a silvicultural planning tool. The overall strategy was to embed the original model within an interactive, programmable graph plotting package. We use a simple interpreted language, with specialised primitives to access internal model data structures, to control model execution and to define and display graphs of model output. These techniques, and our methods of performance optimization and FORTRAN to C conversion, are applicable to simulation models in general. The specification of complex manipulations of model data (representing stand thinning and harvesting operations) is demonstrated.     

A bidirectional heteroassociative memory for binary and grey-level patterns

Typical bidirectional associative memories (BAM) use an offline, one-shot learning rule, have poor memory storage capacity, are sensitive to noise, and are subject to spurious steady states during recall. Recent work on BAM has improved network performance in relation to noisy recall and the number of spurious attractors, but at the cost of an increase in BAM complexity. In all cases, the networks can only recall bipolar stimuli and, thus, are of limited use for grey-level pattern recall. In this paper, we introduce a new bidirectional heteroassociative memory model that uses a simple self-convergent iterative learning rule and a new nonlinear output function. As a result, the model can learn online without being subject to overlearning. Our simulation results show that this new model causes fewer spurious attractors when compared to others popular BAM networks, for a comparable performance in terms of tolerance to noise and storage capacity. In addition, the novel output function enables it to learn and recall grey-level patterns in a bidirectional way.     

CPLD在超声波流量测量系统中的应用

研究了复杂可编程逻辑器件(CPLD)在超声波流量测量系统中的应用。采用高性能的CPLD代替分立元件,实现了液体流量的高精度测量。实验结果表明:应用CPLD技术产生了准确的驱动控制信号,得到了高精度的传播时间计数值,简化了整个电路的设计,提高了系统的稳定性和抗干扰能力。     

A feedback scheduler for real-time controller tasks

The problem studied in this paper is how to distribute computing resources over a set of real-time control loops in order to optimize the total control performance. Two subproblems are investigated: how the control performance depends on the sampling interval, and how a recursive resource allocation optimization routine can be designed. Linear quadratic cost functions are used as performance indicators. Expressions for calculating their dependence on the sampling interval are given. An optimization routine, called a feedback scheduler, that uses these expressions is designed.     

基于FPGA高速图像数据的存储及显示设计

设计了一种基于FPGA控制Nand Flash阵列实现高速流水线式存储的方案。设计利用FPGA作为主控制器,通过Camera Link输入通信接口将图像数据经过一/二级缓存写入Flash存储阵列中,并采用DMA传输技术将存储后的图像数据上传至计算机硬盘中作进一步处理;同时,利用SDRAM显存实时刷新数据,FPGA构造相应的VGA信号,最终实现100 MB/s图像数据的实时显示。     

多核对分区操作系统影响研究

分区操作系统是综合化航空电子领域中的核心技术。随着单核性能极限的到来,处理器结构向着多核发展。将两者结合起来,在多核分区操作系统的基础上研究分析多核处理器结构为分区操作系统带来的影响。经分析实验数据得出多核处理器结构在多核处理器中共享Cache结构和内核中临界资源并发访问两方面对分区操作系统产生影响。     

A multithreaded scheduler for a high-speed spacecraft simulator

The Cassini spacecraft is on its journey to Saturn to perform a close-up study of the Saturnian system; its rings, moons, magneto-sphere, and the planet itself. Sequences of commands will be sent to the spacecraft by ground personnel to control every aspect of the mission. To validate and verify these command sequences, a bit-level, High-Speed Simulator (HSS) has been developed. To maximize performance, the HSS is implemented with multiple threads and runs on a multiprocessor system. A key component of the HSS is the scheduler, which controls the execution of the simulator. The general framework of the scheduler can be adapted to solve a wide variety of scheduling problems. The architecture of the scheduler is presented first, followed by a discussion of issues related to performance and multiple threads. Second, the avoidance of deadlocks and race conditions is discussed, and an informal proof for the absence of both in the scheduler is described. Finally, a study of various scheduling policies is provided. © 1998 John Wiley & Sons, Ltd.     

A hybrid fuzzy and neural approach for DRAM price forecasting

The trend in the price of dynamic random access memory (DRAM) is a very important prosperity index in the semiconductor industry. To further enhance the performance of DRAM price forecasting, a hybrid fuzzy and neural approach is proposed in this study. In the proposed approach, multiple experts construct their own fuzzy multiple linear regression models from various viewpoints to forecast the price of a DRAM product. Each fuzzy multiple linear regression model can be converted into two equivalent nonlinear programming problems to be solved. To aggregate these fuzzy price forecasts, a two-step aggregation mechanism is applied. At the first step, fuzzy intersection is applied to aggregate the fuzzy price forecasts into a polygon-shaped fuzzy number, in order to improve the precision. After that, a back propagation network is constructed to defuzzify the polygon-shaped fuzzy number and to generate a representative/crisp value, so as to enhance the accuracy. A real example is used to evaluate the effectiveness of the proposed methodology. According to experimental results, the proposed methodology improved both the precision and accuracy of DRAM price forecasting by 66% and 43%, respectively.