An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

A silicon bipolar IC for data regeneration and clock recovery which includes a phase/frequency detector (PFD), a quadrature voltage controlled oscillator (VCO), and an MS D-flipflop (DFF) is presented. The VCO is based on a modified two stage ring oscillator approach and presents a wide tuning range of 2-to-9 GHz. Data regeneration at 8 Gb/s (with the onchip VCO) and PFD operation up to 15 Gb/s (with an external VCO) are demonstrated. The IC for clock and data regeneration was fabricated with a 25 GHz f_T 0.4 μm emitter width bipolar process. The power dissipation is 2.25 W     

2.5Gb/s Ga As MESFET定时判决电路

设计了 2 .5 Gb/ s光纤通信用耗尽型 Ga As MESFET定时判决电路 .通过 SPICE模拟表明恢复的时钟频率达2 .5 GHz,判决电路传输速率达 2 .5 Gb/ s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号 ,传输速率达 2 .5 Gb/ s     

Multi-Gb/s silicon bipolar clock recovery IC

A novel clock recovery IC for optical fiber communication systems with data rates up to several Gb/s is presented. It combines nonlinear signal preprocessing directly with a regenerative frequency divider scheme and an external filter in the divider loop. Hence, the center frequency of the filter and the working frequency of the amplifier are halved. The extracted clock frequency corresponds to half the bit rate, as required for many clocked circuit components within fiber optic lines. Two versions of the same IC design, scheduled for two bit rate ranges between 0.3-4 Gb/s, are realized with a conventional Si bipolar process. Clock recovery is demonstrated at 2.2 and 3.52 Gb/s, using both cavity and surface acoustic wave (SAW) filters     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

On the nonlinear behavior of the analog phase-locked loop:synchronization

The synchronization, in the presence of time delay, of a nonlinear analog phase-locked loop (PLL) with an analog multiplier as phase detector (PD) and a lag filter is investigated. A nonlinear model for the voltage-controlled oscillator (VCO) is suggested and the sum frequency component at the PD output is taken into account. Simple expressions of the hold-in range of both the main synchronization and the synchronization at the third harmonic are derived. These expressions point out the effect of the time delay and the filter time constant on the hold-in range. Some conclusions of the presented analysis are not anticipated by the PLL classic theory and allow a better understanding of the loop behavior     

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit

A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-/spl mu/m CMOS process and its die area is 1.1/spl times/0.8 mm/sup 2/. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 2/sup 31/-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 2/sup 7/-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10/sup -12/.     

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 2³¹-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10^-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s     

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50-Ω/5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1-μm gate-length (F_τ=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations     

Bit rate and wavelength transparent all-optical clock recovery scheme for NRZ-coded PRBS signals

All-optical clock recovery from 40-Gb/s nonreturn-to-zero (NRZ) pseudorandom binary sequence data streams based on self-pulsating lasers is presented. A compact preprocessing circuit is utilized to convert an NRZ signal to a pseudoreturn-to-zero sequence before injecting into the optical clock. It comprises a semiconductor optical amplifier followed by a periodical wavelength-division-multiplexing demultiplexer filter. A stable sinusoidal clock signal with a root-mean-square jitter below 700 fs is detected at the output of the self-pulsating laser within data dynamic range of more than 8 dB. The performance of the all-optical clock recovery scheme is investigated by varying the bit rates between 39.81 and 43.02 Gb/s as well as for various wavelengths in the C-band.     

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in×1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA     

QAM全数字接收机载波相位恢复环路

本文着重研究全数字QAM接收机中载波恢复环路的设计，采用快慢两个数字环路来进行载波恢复，慢环路由锁频器（Frequency Detector)，锁频锁相器（Phase and Frequency Detector)等组成，快环路由相痊解旋器和锁相器（Phase Detector)组成，仿真结果表明，在AWGN条件下，两个环路的环路参数设置存在一个最佳点，当两个环路工作在这个最佳点附近时接收机能够很好的进行载波频率，相位的恢复，相位噪声对接收机性能的影响最小，最后，给出了在不同信噪比下的最佳环路参数表。     

C波段锁相变频器模块

设计了一种采用锁相环技术的C波段变频器模块,其原理是输入的信号与压控振荡器(VCO)信号相混频,产生两个信号频率差的信号,这个信号与差频信号IF进行鉴频鉴相,产生的误差信号经环路滤波送入压控振荡器(VCO)的调谐端完成锁相,这时压控振荡器输出的信号就是需要的信号。采用这种技术,模块输出的有用信号与输入信号泄漏到输出端口的功率比在83dB以上,可以达到较好的效果,同时可有效避免使用体积较大的腔体带通滤波器。     

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology. The Pottbacker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.     

A 4 Gb/s 2-level to 2 Gsymbol/s 4-level converter GaAs IC forsemiconductor optical amplifier QPSK modulators

The design of a 50 Ω impedance matched two-to-four level converter GaAs IC for two-electrode semiconductor optical amplifier (SOA) modulators is presented. The designed IC exhibits eye diagrams with eye openings of better than 0.30 V and a spacing between adjacent output signal levels of 0.33 V for output symbol rates of up to 2 Gsymbol/s corresponding to input bit rates of up to 4 Gb/s. A novel differential super buffer output driver is applied, for which output reflection coefficients |S₂₂| of less than -12 dB for frequencies up to 10 GHz are obtained. A 1 Gb/s optical QPSK microwave link transmission experiment using a packaged sample of the designed IC and a two-electrode semiconductor optical amplifier phase modulator has been conducted     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

7.5 Gb/s monolithically integrated clock recovery circuit using PLLand 0.3-μm gate length quantum well HEMT's

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V     

Polarization mode dispersion detected by arrival time measurementof polarization-scrambled light

Polarization mode dispersion (PMD) limits optical fiber capacity. PMD compensators usually minimize the associated eye closure. This measure scales with the square of the differential group delay (DGD) and makes it difficult to detect low DGDs. However, light with a low-speed polarization modulation suffers arrival time variations, in the presence of PMD, that are proportional to the DGD. These are detected by integrating the voltage-controlled oscillator (VCO) input signal of the clock recovery phase-locked loop (PLL). This novel method has been demonstrated for 40 Gb/s nonreturn-to-zero (NRZ) and for 2×40 Gb/s return-to-zero (RZ) polarization division multiplex transmission. PMD detection sensitivities range between 2 ps and 84 fs     

Corona Based Optimal Node Deployment Distribution in Wireless Sensor Networks

This paper shows the trade off between different modulation techniques such as multi level quadrature amplitude modulation, multi level phase shift keying, and multi level differential phase shift keying for upgrading direct detection optical orthogonal frequency division multiplexing systems with possible transmission distance up to 15,000 km and total bit rate of 2.56 Tb/s. The 2.56 Tb/s signal is generated by multiplexing 64 OFDM signals with 40 Gb/s for each OFDM. Variations of optical signal to noise ratio (OSNR), signal to noise ratio (SNR), and bit error rate (BER) are studied with the variations of transmission distance. Maximum radio frequency power spectrum, and output electrical power after decoder are measured for different multi level modulation techniques with carrier frequency. It is observed that multi level QAM has presented better performance than multi level PSK and finally multi level DPSK in optical OFDM systems. Maximum output power after decoder is enhanced with both 32-PSK, and 64-QAM. Quadrature signal amplitude level at encoder is upgraded with 64-QAM. It is noticed that OSNR, SNR, and BER are improved using 4-QAM OFDM system than either QPSK or 4-DPSK.     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.