用于电路模拟的4H-SiC MOSFET高温沟道电子迁移率模型

提出了适用于电路模拟的4H-SiC n-MOSFET高温沟道电子迁移率模型.在新模型中,引入了横向有效电场和表面粗糙散射的温度依赖性,电子饱和漂移速度与横向有效电场和温度的关系,以及改进的界面陷阱电荷和固定氧化物电荷库仑散射模型等因素.采用与温度-阈值电压实验曲线拟合的方法,确定了界面态参数和固定氧化物电荷.基于新迁移率模型的模拟结果与实验吻合.     

6H-SiC反型层电子迁移率的MonteCarlo模拟

用单电子Monte Carlo方法对6H-SiC反型层的电子迁移率进行了模拟,在模拟中采用了一种新的综合的库仑散射的模型,该模型考虑了栅氧化层电荷、界面态电荷、沟道电离杂质电荷的作用以及它们之间的相关性.Monte Carlo模拟的结果表明,当表面有效横向电场高于1.5×10⁵V/cm时,表面粗糙散射在SiC反型层中起主要作用,而当有效横向电场小于该值时,沟道散射以库仑散射为主.     

应变Si/SiO2界面对NMOS沟道电子迁移率的影响研究

本文提出全新的半经验应变Si NMOS反型沟道电子迁移率模型,此模型考虑了晶格散射,离化杂质散射,表面声子散射,界面电荷散射以及界面粗糙散射等散射机制对反型沟道电子迁移率的影响,并考虑了反型层电子的屏蔽效应。利用Matlab软件对所建模型进行了模拟,模拟结果与实验数据符合较好。     

AlGaN/GaN异质结辐射感生界面态电荷对二维电子气输运的影响

根据荷电中心与自由载流子间的库仑散射作用,给出了异质结辐射感生界面态电荷对二维电子气(2DEG)迁移率的散射模型.计算了在不同沟道电子面密度下,界面态电荷密度与其所限制的迁移率之间的关系.运用马德森定则分析了辐射感生界面态电荷散射对总迁移率的影响.分析表明,辐射感生界面态电荷在累积到一定量后,会显著影响迁移率,一定程度上提高2DEG密度能抑制界面态电荷散射的作用.     

AlGaN/GaN异质结辐射感生界面态电荷对二维电子气输运的影响

根据荷电中心与自由载流子间的库仑散射作用,给出了异质结辐射感生界面态电荷对二维电子气(2DEG)迁移率的散射模型.计算了在不同沟道电子面密度下,界面态电荷密度与其所限制的迁移率之间的关系.运用马德森定则分析了辐射感生界面态电荷散射对总迁移率的影响.分析表明,辐射感生界面态电荷在累积到一定量后,会显著影响迁移率,一定程度上提高2DEG密度能抑制界面态电荷散射的作用     

高剂量辐照条件下的MOSFET总剂量辐照效应模型

报道了一种用于在高剂量辐照条件下MOS器件抗辐照电路模拟的半经验模型.利用该模型对MOS器件实验结果进行了模拟,模型计算结果与实验吻合较好.初步分析了高剂量条件下不同散射机制对模拟结果的影响,结果表明界面电荷的库仑散射是引起电子迁移率退化的主要机制.     

高剂量辐照条件下的MOSFET总剂量辐照效应模型

报道了一种用于在高剂量辐照条件下 MOS器件抗辐照电路模拟的半经验模型 .利用该模型对 MOS器件实验结果进行了模拟 ,模型计算结果与实验吻合较好 .初步分析了高剂量条件下不同散射机制对模拟结果的影响 ,结果表明界面电荷的库仑散射是引起电子迁移率退化的主要机制     

SiO2/SiC界面对4H-SiC n-MOSFET反型沟道电子迁移率的影响

提出了一种基于器件物理的4H-SiC n-MOSFET反型沟道电子迁移率模型.该模型包括了界面态、晶格、杂质以及表面粗糙等散射机制的影响,其中界面态散射机制考虑了载流子的屏蔽效应.利用此模型,研究了界面态、表面粗糙度等因素对迁移率的影响,模拟结果表明界面态和表面粗糙度是影响沟道电子迁移率的主要因素.其中,界面态密度决定了沟道电子迁移率的最大值,而表面粗糙散射则制约着高场下的电子迁移率.该模型能较好地应用于器件模拟.     

SiO_2/SiC界面对4H-SiC n-MOSFET反型沟道电子迁移率的影响

提出了一种基于器件物理的4 H- Si C n- MOSFET反型沟道电子迁移率模型.该模型包括了界面态、晶格、杂质以及表面粗糙等散射机制的影响,其中界面态散射机制考虑了载流子的屏蔽效应.利用此模型,研究了界面态、表面粗糙度等因素对迁移率的影响,模拟结果表明界面态和表面粗糙度是影响沟道电子迁移率的主要因素.其中,界面态密度决定了沟道电子迁移率的最大值,而表面粗糙散射则制约着高场下的电子迁移率.该模型能较好地应用于器件模拟.     

MOS结构γ总剂量效应仿真模型研究

研究了对MOS结构的γ射线总剂量辐射效应进行Sentaurus TCAD仿真所需模型的有效性.仿真结果表明,Sentaurus TCAD提供的Radiation模型和Traps模型在氧化物中并不能被激活,而利用激活氧化物体区和Si/SiO2界面的Insulator Fixed Charges模型可以分别对γ总剂量辐射造成的氧化层固定电荷和Si/SiO2界面陷阱电荷进行有效的模拟仿真.     

A comprehensive model for inversion layer hole mobility forsimulation of submicrometer MOSFET's

A comprehensive model of effective (average) mobility and local-field mobility for holes in MOSFET inversion layers is presented. The semiempirical equation for effective mobility, coupled with the new local-field mobility model, permits accurate two-dimensional simulation of source-to-drain current in MOSFETs. The model accounts for the dependence of mobility on transverse and longitudinal electric fields, channel doping concentration, fixed interface charge density, and temperature. It accounts not only for the scattering by fixed interface charges, and bulk and surface acoustic phonons, but it also correctly describes screened Coulomb scattering at low effective transverse fields (near threshold) and surface roughness scattering at high effective transverse fields. The model is therefore applicable over a much wider range of conditions compared to earlier reported inversion layer hole mobility models while maintaining a physically based character     

A new hole mobility model for hydrodynamic simulation

A new self-consistent hole mobility model that includes the lattice and the hole temperature has been proposed. By including the lattice and hole temperatures as well as the effective transverse field and the interface fixed charge, the model predicts the saturation of the hole drift velocity and shows the effects of Coulomb scattering, surface phonon scattering, and surface roughness scattering. The model has been incorporated into a device simulation program, SNU-2D. The simulation results have been compared with the reported experimental data and the measured 0.1 μm pMOSFETs, and they are shown to agree quite well. The new model is expected to estimate the characteristics of very short-channel devices in the hydrodynamic model simulations.     

MOSFET electron inversion layer mobilities-a physically basedsemi-empirical model for a wide temperature range

A physically based semiempirical model for electron mobilities of the MOSFET inversion layers that is valid over a large temperature range (77 K⩽T⩽370 K) is discussed. It is based on a reciprocal sum of three scattering mechanisms, i.e. phonon, Coulomb, and surface roughness scattering, and is explicitly dependent on temperature and transverse electric field. The model is more physically based than other semiempirical models, but has an equivalent number of extracted parameters. It is shown that this model compares more favorably with the experimental data than previous models. The implicit dependencies of the model parameters on oxide charge density and surface roughness are confirmed     

pMOS器件NBTI界面电荷引起耦合的数值模拟分析

从二维模拟pMOS器件得到沟道空穴浓度和栅氧化层电场,用于计算负栅压偏置温度不稳定性NBTI(Negative bias temperature instability)效应的界面电荷的产生,是分析研究NBTI可靠性问题的一种有效方法。首先对器件栅氧化层/硅界面的耦合作用进行模拟,通过大量的计算和已有的实验比对分析得出:当NBTI效应界面电荷产生时,栅氧化层电场是增加了,但并没有使界面电荷继续增多,是沟道空穴浓度的降低决定了界面电荷有所减少(界面耦合作用);当界面电荷的产生超过1012/cm2时,界面的这种耦合作用非常明显,可以被实验测出;界面耦合作用使NBTI退化减小,是一种新的退化饱和机制,类似于"硬饱和",但是不会出现强烈的时间幂指数变化。     

Influence of the interface-state density on the electron mobility in silicon inversion layers

The electron inversion-layer mobility in a metal oxide semiconductor field effect transistor, as a function of the transverse electric field, has been studied in the temperature range 13–300K for different interface-state densities. Experimental data are in excellent agreement with a simple semi-empirical model. However, the term attributed by other authors to phonon scattering depends on the interface-state density, even at high temperatures, and becomes negative at low temperatures. These facts are shown to be a consequence of the dependence of coulomb scattering on the transverse electric field.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

Experimental investigation of N-MOS inversion layers in the electric quantum limit

In this paper we report on the experimental determination of inversion electron charge density, silicon surface potential, and effective electron mobility vs oxide electric field, for NMOSFETs with gate oxide thickness Tox = 2.2 nm operating far beyond the limit of applicability of Boltzmann relationships in the inversion layer. We find that such oxides have the same values of destructive breakdown electric field, dielectric constant, and trap density at the silicon-oxide interface as “thick” oxides.     

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.