OC门的变通应用

OC 门又称集电极开路门,它与一般门电路的区别就在于它的输出管集电极是开路的,集电极的负载电阻由外电路决定。利用 OC 门的这一结构特点,可在某些场合使用时简化电路设计,扩展逻辑功能,起到一般门电路不能实现的功能。(一)作“线与”联接一般来说,TTL 门电路是不允许将输出端互相直接连接的,否则当其中一个门输出为高电平而其它门输出为     

BiCMOS三态输出门电路的设计、制备及应用

设计了几种BiCMOS三态输出门电路,提出了采用先进的0.5μm BiCMOS工艺,制备所设计的三态输出门的技术要点和器件参数,并分析了它们既具有双极型(Bipolar)门电路快速、大电流驱动能力,又具备CMOS逻辑门低压、低功耗和高集成度的特性,因而它们特别适用于高速缓冲数字信息系统和其它便携式数字设备中.     

如何判别数字电路的好坏

<正> 门电路和触发器是构成数字电路的两大单元电路。在选购与使用之前,有必要对门电路和触发器好坏进行判别。下面介绍判别门电路和触发器好坏的两种简单方法,供读者参考。 1.判别门电路好坏的方法 门电路的好坏是根据不同门电路的逻辑特性来判别的。现以图1所示的CMOS“与非”门CD4011为例来加以说明。“与非”门的逻辑特性是:当所有的输入端全部为高电平时,输出为低电平,即“全高出低”;而只要有一个输入端为低电平,输出就为高电平,即“有低出高”。CMOS电路供电电压     

一种理解和设计传输门逻辑和静态CMOS门逻辑电路的方法

在充分了解NMOS管和PMOS管电学特性的基础上,我们总结了一个理解和设计传输门逻辑和静态CMOS门逻辑电路的方法,这种方法能够简单易懂的去理解基于MOS器件的传输门和静态CMOS门逻辑电路。运用这种方法,我们也可以方便的去设计传输门和静态CMOS门逻辑电路。我们的方法将静态逻辑门电路和传输门逻辑电路有机的统一起来,便于理解学生的理解和记忆。     

CMOS数字集成电路原理与应用（二）

二、CMOS非门及其应用门电路是数字电路基本形式之一。门电路大致有与门、或门、非门、与非门、或非门、与或非门、异或门等多种形式。其中,非门是CMOS电路的最基本单元,亦称作反相器。在逻辑关系中,非门是指这个门电路的输入输出关系是相反的。图1是非门的逻辑图形符号。A是输入端,P是输出端,其逻辑表达式为P=。“非”的逻辑关系一律采用空心小圆。附表为非门的逻辑关系。     

一种分析MOS集成门内部电路的简易方法

在介绍了MOS反相器,与非门、或非门后,对那些规范的MOS门电路,学生可以将其分解成若干基本关系,从而分析写出电路的逻辑表达式,但对一些特殊结构的MOS门电路,学生则束手无策.针对这种情况,我们给同学介绍了一种简易的分析方法.本文中,暂且称之为“见驱动管就非法”以便记忆.分析图1所示电路,可见T_2是等效负载,T_1是驱动管,根据工作原理可列出其真值     

简单逻辑门电路学习方法初探

逻辑门是集成电路上的基本组件,逻辑门电路是当前数字电路广泛应用的重要前提和基础,它是不单是物理教育的重要组成部分,更是电子电器和计算机等相关专业的基础知识。由于逻辑电路要领功能繁多,记忆复杂,不易于掌握,学习起来容易感到力不从心。本文介绍了逻辑门电路的基本概念及表示方法,用类比的方法对逻辑门电路的规律进行总结,最后重点阐述逻辑门电路的实际应用。     

电路之美CD4069制作按键开关

初识逻辑门 大家好,今天开始我们来研究逻辑门电路。什么是逻辑门电路呢？从名字上看“逻辑门”应该是指有逻辑关系的门．门应该是种比喻．表示这种电路和门有着相同的特点。如果在名字里直接写上特点会显得太长,而用类似的事物代替既简洁又形象。那“门”有什么特点呢？     

第五章 动态逻辑电路

在MOS集成电路中,按工作方式来说,还可以分为静态逻辑电路和动态逻辑电路两类。在前几章介绍的各种逻辑门电路,组合电路和触发器都属于静态逻辑电路。所谓静态逻辑,就是指逻辑电路可以在很低的频率下工作,或就在直流的情况下工作。例如,如果在静态反相器的输入加一个直流低电平,反相器将稳定地输出一个直流高电平;又如静态触发器可以长时间地处于一个稳定状态。而动态逻输电路就不同,它只允许在交流情况下工作。一般地说,电路中页载管     

MOS电流模逻辑加法器结构设计

为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的开关条件以及具有不同输入端的MCML逻辑门电路进行分析后,提出了实现MCML加法器的两种电路结构,并给出了不同结构的应用条件.仿真结果验证了电路结构设计的有效性.     

Silicon-on-Sapphire Complementary MOS Memory Cells

Complementary MOS circuitry offers the advantages of high-speed, low-quiescent power dissipation, and loose device parameter tolerances. However, only with the recent development of clean technology has it been possible to fabricate stable devices. The advances in silicon-on-sapphire epitaxy have permitted the development of a high-speed low-power complementary MOS circuit module. This paper describes the circuit, its operation, the method used in fabricating it in silicon-on-sapphire, and the switching performance of the circuit. The basic memory cell is a NDRO flip-flop with feedback supplied through a transmission gate. The total circuit delay from write command to output sense signal is 5 to 7 ns at a standby power dissipation of 7 to 20 /spl mu/ W. To show the feasibility of adapting silicon-on-sapphire complementary MOS technology to LSI, a 9-bit word (1-byte) was constructed. The entire module containing 54 N-channel and 36 P-channel devices dissipated less than 100 /spl mu/ W in a standby condition.     

U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ)operation

Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance to the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum ρ-τ product of 3 fJ/gate has been obtained for a design rule of 1-μm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a ρ-τ product of 350 fJ/gate     

Low-power chip interconnection by dynamic termination

A low-power dynamic termination scheme is proposed and demonstrated as a way to reduce power dissipation for high-speed data transport. In this scheme, the transmission lines are terminated only if the signals change. The gate of a switching MOS transistor connected to a termination resistor is driven by differentiating the transmission signal with a resistor and a capacitor. The power dissipation of the terminating resistor can be reduced to 1/5 in the conventional determination scheme, and overshoot can be reduced to 1/5 that in the open scheme. This scheme is promising for use with palm-top equipment, facilitating high-speed low power operation     

Femtojoule high speed planar GaAs E-JFET logic

An integrated inverter stage operating in the gigabit range at a static power dissipation of 100 µW was built for future use in LSI logic circuits. Planar gallium arsenide technology was employed using selective ion-implanted enhancement mode junction field-effect transistors (E-JFET) having 3-µm gate lengths. A nine-stage ring oscillator served as a test vehicle to assess the speed-power product for digital applications. A theoretical analysis shows the transistor operates during the switching transient in the saturation regime, notwithstanding steady-state operation in the linear regime. When the transistor is switched off, the transient response is governed by the load resistance and the input capacitance of the subsequent stage. Means of reducing the switching time by increasing the supply voltage, nonlinear load devices, an output buffer stage, and reduction of gate length and width are described. Directly coupled E-JFET logic does not require level shifting, and, therefore, offers advantages over depletion-mode gallium arsenide MESFET logic by reducing the number of circuit elements per gate. Projected gallium arsenide E-JFET LSI logic circuits will surpass silicon-based bipolar logic with respect to both speed and power, and n-channel silicon MOS logic with respect to speed.     

High gain power switching using field controlled thyristors

A technique for high gain power switching using field controlled thyristors is described. This technique uses a MOSFET connected in series with the FCT to control the current flow. The circuit exhibits normally-off behavior and is capable of operation at high voltages. The current through the FCT can be turned on and off by the application of a low voltage gate signal to the MOSFET. Turn-on and turn-off times of less than 1 μs have been observed at a current gain of over 30. The new gating technique offers the advantage of the large operating current density of the FCT even at high breakdown voltages and the high input impedance of the MOS gate used to trigger the device during power switching.     

Transient Analysis of Four-Phase MOS Switching Circuits

Four-phase MOS switching circuits lend themselves readily to utilization on large-scale integrated arrays and possess many attractive and practical features. A model for transient analysis is presented. The evaluation and analysis of a generalized four-phase MOS gate which can implement a complex logic function are discussed.     

Switching characteristic of MOS differential pair with mismatched transistors

The switching characteristic of a differential pair with mismatched MOS transistors is obtained in a convenient form. The characteristic represents the difference between the transistor gate voltages as a function of the difference between the drain currents. When the differences are small the differential pair trans-conductance and offset voltage are easily found.     

Analysis and design of the dual-gate inversion layer emitter transistor

The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.     

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200 V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1 V even after 2000 h of serious gate voltage stresses of + 25 V and − 10 V at 150 °C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000 h under the drain voltage of 1200 V at 150 °C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.