Stuck-open testable scan-based CMOS sequential circuits

A testing methodology for applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits is presented. This method requires shifting in only one pattern and requires no special latches in the scan chain. Sufficient conditions for robust testability of all single field-effect transistor (FET) stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. This technique leads to realizations with at most two additional inputs and some additional FET's in the first-level gates     

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.     

Highly testable design of BiCMOS logic circuits

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15%     

Computer-aided design and characterization of digital MOS integrated circuits

A computer-aided circuit-simulation method is developed to enable the design, characterization, and optimization of MOS integrated circuits. The computation of dc and transient characteristics is done in terms of physical device parameters extracted from processing information and incorporated in an analytical device model. It is demonstrated that any MOS circuit configuration (with its associated series resistances and parasitic devices) can be analyzed in terms of an equivalent inverter. Input-output transfer characteristics are obtained by superposition of the load and transistor I-V characteristics, providing the necessary information for dc > `worst-case' design. A simple device model was used to compute circuit transient response. All the computed characteristics are in good agreement with measurements performed on integrated circuits.     

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.     

Monolithic CMOS digital integrated circuits in 6H-SiC using animplanted p-well process

We report the first p-well Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits in 6H-SiC. Enhancement mode NMOSFET's and PMOSFET's are fabricated on implanted p-wells and n-type epilayers, respectively. CMOS logic circuits such as inverters, NAND, NOR, XOR, flip-flops, half adders, and 11-stage ring oscillators are implemented using these devices and operated at room temperature, The inverters show stable operation at room temperature and 300°C with V_dd=10 and 15 V     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.     

On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-μm CMOS technology exhibit a 100% delay increase in a long coupled line configuration     

Noise in digital dynamic CMOS circuits

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits     

GaAs IGFET digital integrated circuits

A technique to utilize GaAs insulated gate field effect transistors (IGFEI's) with large surface state densities in digital integrated circuits is described. In this technique, the threshold voltage is electrically set to obtain enhancement-mode characteristics of the IGFET's. Due to change in surface charge with time, these circuits will not function at very low frequencies. Several advantages of this IGFET technology over other enhancement-mode GaAs technologies are presented.     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Process technology for radiation-hardened CMOS integrated circuits

A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.     

Minimizing power consumption in digital CMOS circuits

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

Battery-powered digital CMOS design

In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a superlinear function of the average discharge current. Next we show that even if the average discharge current remains the same, different discharge current profiles (distributions) may result in very different battery lifetimes. In particular, the maximum battery life is achieved when the variance of the discharge current distribution is minimized. Analytical derivations and experimental results underline the importance of the correct modeling of the battery-hardware system as a whole and provide a more accurate basis (i.e., the battery discharge times delay product) for comparing various low-power optimization methodologies and techniques targeted toward battery-powered electronics. Finally, we calculate the optimal value of V/sub dd/ for a battery-powered VLSI circuit so as to minimize the product of the battery discharge times circuit delay.     

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption