Random telegraph noise of deep-submicrometer MOSFETs

The random telegraph noise exhibited by deep-submicrometer MOSFETs with very small channel area (⩽1 μm²) at room temperature is studied. Analysis of the amplitude of the current fluctuations reveals that the trapped charges generate noise through modulation of the carrier mobility in addition to the carrier number. Parameters needed for modeling the carrier mobility fluctuation effect on the flicker noise in conventional MOSFETs are extracted directly from the random telegraph noise data     

Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Cost-effective smart power CMOS/DMOS technology: design of main driving and protection functions

This paper intends to show that even with a CMOS technology main driving and protection functions of a power VDMOS can be made performant. Original circuits taking advantage of the availibility of the parasitic vertical bipolar transistor are presented and experimentally evaluated. A current mode approach is proposed to improve the accuracy of the current sensing function aimed at performing overcurrent, short-circuit and open-load detection.     

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Temperature distribution in diced and packaged DMOS devices subjected to repetitive stress is analyzed using transient interferometric mapping (TIM) technique combined with measurements on diode built-in temperature sensors. The effect of DMOS device position on dice, duty cycle and chip ambient temperature on thermal distribution is studied. The TIM experiments and transient temperature measurements are in good agreement with numerical 3D thermal simulations. Failure analysis data after long term pulse stress testing indicate electromigration degradation of the top metal.     

Reliability of smart power devices

Smart power devices of the last generation are able to integrate a full electronic system, including logic and analog functions and power drivers, in a true single chip solution exploiting the advanced features made available by mixed BCD processes developed for this purpose. The complexity of the ICs and their applications together with the severe stress conditions which these devices can experience in the field makes the reliability assurance of the Smart Power ICs a very challenging task and for this purpose a complete approach is necessary combining an application oriented IC qualification methodology with structural evaluations to test the intrinsic reliability of the basic process elements. In this context the knowledge of the main failure mechanisms is fundamental both for an effective detection in qualification and for an early prevention during IC design.     

Random telegraph signal noise instabilities in lattice-mismatched InGaAs/InP photodiodes

Spontaneous and induced instabilities in the character of Random Telegraph Signal (RTS) noise are studied in photodetector arrays, fabricated on lattice-mismatched InGaAs/InP heterostructures. The disappearance and reappearance of the RTS noise as well as abrupt changes in the RTS noise amplitude and pulse complexity are investigated as a function of voltage and temperature. The RTS noise instabilities are explained in terms of structural transformation of complex multistable crystalline defects.     

Random telegraph signal currents and low-frequency noise injunction field effect transistors

The detailed study of random telegraph signal (RTS) currents and low-frequency (LF) noise in semiconductor devices in recent years has confirmed their cause and effect relationship. In this paper we describe the physical mechanisms responsible for RTS currents in any device. The methods for calculating the amplitudes and characteristic times of the RTS currents produced by traps with known electrical characteristics and locations are described. The noise spectra in junction field effect transistors (JFET's) resulting from traps in the silicon or the oxide are derived as a function of basic device parameters, operating conditions and temperature. Experimental results verifying the predictions of the models are presented     

Analysis of lateral DMOS power devices under ESD stress conditions

The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogeneous current flow due to the unusual electrical behavior are accurately analyzed in single- and multi-finger devices     

Hot-carrier-induced off-state current leakage in submicrometerPMOSFET devices

Hot-carrier-induced off-state leakage (HCIOL) currents were successfully used as a new monitor in characterizing device reliability. HCIOL current increases drastically with reducing channel length, but the stress bias only affects the onset time of HCIOL current. For buried-channel PMOSFET's, only the HCIOL currents at the reverse measurement configuration were dominant. However, in surface-channel devices, HCIOL currents at both forward and reverse configurations became important. An empirical HCIOL current model was developed to quantify device lifetime as a function of channel length and stress voltage. Estimated lifetime results indicated that HCIOL current will impose a major limit on device reliability especially for deep-submicrometer technology and low power applications     

Determining the drain doping in DMOS transistors using the hump inthe leakage current

The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers     

Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit

In this paper, we present extensive random telegraph signal (RTS) noise characterization in SiGe heterojunction bipolar transistors. RTS noise, observed at the base, originates at the emitter periphery while at the collector side distinct RTS noise is observed at high-injection that originates from the traps in the shallow trench regions. Time constants extracted from RTS during aging tests allow understanding of trap dynamics and new defect formation within the device structure. This paper provides the first demonstration of RTS measurements during accelerated aging tests to study and understand generation of defects under bias stress in SiGe HBTs operating at the limit of their safe-operating area.     

基于智能整流技术的电网电流谐波补偿方法研究

目前用于电网电流谐波补偿的电器设备,主要以PWM整流器为主。基于PWM整流器的电源产品只能被动地减小自身向电网输出的谐波电流,而对电网中业已存在的电流谐波污染束手无策。为了解决电网中电流谐波污染以及相关联的电压波形失真问题,采用基于SRM(智能整流模块)技术对电网电流谐波进行补偿。仿真结果表明,基于SRM的电力电子装置在从电网吸取电流并在向负载供电的同时,还能对电网电压的波形进行补偿,使电网电压波形接近正弦波形。     

Automated setup for thermal imaging and electrical degradation study of power DMOS devices

An automated setup for investigation of degradation mechanisms in semiconductor devices under electrostatic discharge (ESD) stress is presented. Vertical-DMOS transistors of a Smart Power technology operating in bipolar snapback mode are studied by combined techniques. The current filamentary behavior imaged by a two-instants transient interferometric mapping (TIM) method and the variation of device DC characteristics are studied as a function of stress current. During repeated stress, a progressive degradation of the DC leakage current at the failure level and a slight gradual change of transfer characteristics are observed. The failure location, resolved in three dimensions by backside infrared microscopy, agrees with the position obtained from the TIM analysis and expected from device physics.     

怎样获得出色的集成功率器件

“智能功率”和“集成功率器件”等词汇已经被用滥了,而且其定义也非常含糊。本文中所指的“智能功率”或“集成功率器件”是已封装的器件,能完成信号处理和功率处理功能。     

The optimization of on-resistance in vertical DMOS power devices with linear and hexagonal surface geometries

The on-resistance-area product is calculated for VDMOS high-voltage transistors by three different techniques. The two simpler analytic approaches provide useful approximations to the more accurate simulation. The sheet resistance of the accumulation layer is taken into account and gives rise to an optimum source spacing for minimum on-resistance. Linear and hexagonal surface geometries are compared. The latter is shown to give lower R . A products at certain values of source spacing, but higher values if the source spacing exceeds a critical value.     

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate     

An overview of smart power technology

The evolution of smart power technology and the impact of this technology on electronic systems are reviewed. After providing a definition of smart power technology, the author describes the key technological developments in power semiconductor devices, namely power MOSFETs and IGBTs (insulated-gate bipolar transistors). These developments are the foundation upon which smart power technology rests. Smart power technology requires the marriage of power device technology with CMOS logic and bipolar analog circuits. The technical challenges involved in combining power handling capability with on-chip regulation of overcurrent, overvoltage, and overtemperature conditions are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies     

Random telegraph signals in deep submicron n-MOSFET's

Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO₂ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel